Sequencer.cc revision 11049
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 2910467Sandreas.hansson@arm.com#include "arch/x86/ldstflags.hh" 308229Snate@binkert.org#include "base/misc.hh" 317056Snate@binkert.org#include "base/str.hh" 327632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 338232Snate@binkert.org#include "debug/MemoryAccess.hh" 348232Snate@binkert.org#include "debug/ProtocolTrace.hh" 358615Snilay@cs.wisc.edu#include "debug/RubySequencer.hh" 369104Shestness@cs.utexas.edu#include "debug/RubyStats.hh" 378615Snilay@cs.wisc.edu#include "mem/protocol/PrefetchBit.hh" 388615Snilay@cs.wisc.edu#include "mem/protocol/RubyAccessMode.hh" 397039Snate@binkert.org#include "mem/ruby/profiler/Profiler.hh" 408229Snate@binkert.org#include "mem/ruby/slicc_interface/RubyRequest.hh" 416154Snate@binkert.org#include "mem/ruby/system/Sequencer.hh" 426154Snate@binkert.org#include "mem/ruby/system/System.hh" 437550SBrad.Beckmann@amd.com#include "mem/packet.hh" 4410467Sandreas.hansson@arm.com#include "sim/system.hh" 456876Ssteve.reinhardt@amd.com 467055Snate@binkert.orgusing namespace std; 477055Snate@binkert.org 486876Ssteve.reinhardt@amd.comSequencer * 496876Ssteve.reinhardt@amd.comRubySequencerParams::create() 506285Snate@binkert.org{ 516876Ssteve.reinhardt@amd.com return new Sequencer(this); 526285Snate@binkert.org} 537039Snate@binkert.org 546876Ssteve.reinhardt@amd.comSequencer::Sequencer(const Params *p) 5510012Snilay@cs.wisc.edu : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) 566876Ssteve.reinhardt@amd.com{ 576876Ssteve.reinhardt@amd.com m_outstanding_count = 0; 586285Snate@binkert.org 596876Ssteve.reinhardt@amd.com m_instCache_ptr = p->icache; 606876Ssteve.reinhardt@amd.com m_dataCache_ptr = p->dcache; 6111019Sjthestness@gmail.com m_data_cache_hit_latency = p->dcache_hit_latency; 6211019Sjthestness@gmail.com m_inst_cache_hit_latency = p->icache_hit_latency; 636876Ssteve.reinhardt@amd.com m_max_outstanding_requests = p->max_outstanding_requests; 646876Ssteve.reinhardt@amd.com m_deadlock_threshold = p->deadlock_threshold; 656899SBrad.Beckmann@amd.com 666876Ssteve.reinhardt@amd.com assert(m_max_outstanding_requests > 0); 676876Ssteve.reinhardt@amd.com assert(m_deadlock_threshold > 0); 686876Ssteve.reinhardt@amd.com assert(m_instCache_ptr != NULL); 696876Ssteve.reinhardt@amd.com assert(m_dataCache_ptr != NULL); 7011019Sjthestness@gmail.com assert(m_data_cache_hit_latency > 0); 7111019Sjthestness@gmail.com assert(m_inst_cache_hit_latency > 0); 728171Stushar@csail.mit.edu 738171Stushar@csail.mit.edu m_usingNetworkTester = p->using_network_tester; 746145Snate@binkert.org} 756145Snate@binkert.org 767039Snate@binkert.orgSequencer::~Sequencer() 777039Snate@binkert.org{ 786145Snate@binkert.org} 796145Snate@binkert.org 807039Snate@binkert.orgvoid 817039Snate@binkert.orgSequencer::wakeup() 827039Snate@binkert.org{ 8310913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Draining); 849245Shestness@cs.wisc.edu 857039Snate@binkert.org // Check for deadlock of any of the requests 869501Snilay@cs.wisc.edu Cycles current_time = curCycle(); 876145Snate@binkert.org 887039Snate@binkert.org // Check across all outstanding requests 897039Snate@binkert.org int total_outstanding = 0; 906285Snate@binkert.org 917455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 927455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 937455Snate@binkert.org for (; read != read_end; ++read) { 947455Snate@binkert.org SequencerRequest* request = read->second; 957455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 967455Snate@binkert.org continue; 977455Snate@binkert.org 987805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 9911025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_readRequestTable: %d " 10011025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 10111025Snilay@cs.wisc.edu request->pkt->getAddr(), m_readRequestTable.size(), 1029467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1039467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1046145Snate@binkert.org } 1056145Snate@binkert.org 1067455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1077455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1087455Snate@binkert.org for (; write != write_end; ++write) { 1097455Snate@binkert.org SequencerRequest* request = write->second; 1107455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 1117455Snate@binkert.org continue; 1127455Snate@binkert.org 1137805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 11411025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 11511025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 11611025Snilay@cs.wisc.edu request->pkt->getAddr(), m_writeRequestTable.size(), 1179467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1189467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1196145Snate@binkert.org } 1206285Snate@binkert.org 1217039Snate@binkert.org total_outstanding += m_writeRequestTable.size(); 1227039Snate@binkert.org total_outstanding += m_readRequestTable.size(); 1236145Snate@binkert.org 1247039Snate@binkert.org assert(m_outstanding_count == total_outstanding); 1257039Snate@binkert.org 1267039Snate@binkert.org if (m_outstanding_count > 0) { 1277039Snate@binkert.org // If there are still outstanding requests, keep checking 1289465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1297039Snate@binkert.org } 1306145Snate@binkert.org} 1316145Snate@binkert.org 13210012Snilay@cs.wisc.eduvoid Sequencer::resetStats() 1339598Snilay@cs.wisc.edu{ 13410012Snilay@cs.wisc.edu m_latencyHist.reset(); 13510012Snilay@cs.wisc.edu m_hitLatencyHist.reset(); 13610012Snilay@cs.wisc.edu m_missLatencyHist.reset(); 1379773Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 13810012Snilay@cs.wisc.edu m_typeLatencyHist[i]->reset(); 13910012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->reset(); 14010012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->reset(); 1419773Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 14210012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->reset(); 14310012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->reset(); 1449773Snilay@cs.wisc.edu } 1459773Snilay@cs.wisc.edu } 1469773Snilay@cs.wisc.edu 14710012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 14810012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->reset(); 14910012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->reset(); 1509773Snilay@cs.wisc.edu 15110012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->reset(); 15210012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->reset(); 15310012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->reset(); 15410012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->reset(); 1559773Snilay@cs.wisc.edu 1569773Snilay@cs.wisc.edu m_IncompleteTimes[i] = 0; 1579773Snilay@cs.wisc.edu } 1589598Snilay@cs.wisc.edu} 1599598Snilay@cs.wisc.edu 1607039Snate@binkert.orgvoid 1617039Snate@binkert.orgSequencer::printProgress(ostream& out) const 1627039Snate@binkert.org{ 1637039Snate@binkert.org#if 0 1647039Snate@binkert.org int total_demand = 0; 1657039Snate@binkert.org out << "Sequencer Stats Version " << m_version << endl; 16610919Sbrandon.potter@amd.com out << "Current time = " << m_ruby_system->getTime() << endl; 1677039Snate@binkert.org out << "---------------" << endl; 1687039Snate@binkert.org out << "outstanding requests" << endl; 1696145Snate@binkert.org 1707455Snate@binkert.org out << "proc " << m_Read 1717455Snate@binkert.org << " version Requests = " << m_readRequestTable.size() << endl; 1726145Snate@binkert.org 1737039Snate@binkert.org // print the request table 1747455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 1757455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 1767455Snate@binkert.org for (; read != read_end; ++read) { 1777455Snate@binkert.org SequencerRequest* request = read->second; 1787039Snate@binkert.org out << "\tRequest[ " << i << " ] = " << request->type 1797039Snate@binkert.org << " Address " << rkeys[i] 1807039Snate@binkert.org << " Posted " << request->issue_time 1817039Snate@binkert.org << " PF " << PrefetchBit_No << endl; 1826145Snate@binkert.org total_demand++; 1837039Snate@binkert.org } 1846145Snate@binkert.org 1857455Snate@binkert.org out << "proc " << m_version 1867455Snate@binkert.org << " Write Requests = " << m_writeRequestTable.size << endl; 1876285Snate@binkert.org 1887039Snate@binkert.org // print the request table 1897455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1907455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1917455Snate@binkert.org for (; write != write_end; ++write) { 1927455Snate@binkert.org SequencerRequest* request = write->second; 1937039Snate@binkert.org out << "\tRequest[ " << i << " ] = " << request.getType() 1947039Snate@binkert.org << " Address " << wkeys[i] 1957039Snate@binkert.org << " Posted " << request.getTime() 1967039Snate@binkert.org << " PF " << request.getPrefetch() << endl; 1977039Snate@binkert.org if (request.getPrefetch() == PrefetchBit_No) { 1987039Snate@binkert.org total_demand++; 1997039Snate@binkert.org } 2007039Snate@binkert.org } 2017039Snate@binkert.org 2027039Snate@binkert.org out << endl; 2037039Snate@binkert.org 2047039Snate@binkert.org out << "Total Number Outstanding: " << m_outstanding_count << endl 2057039Snate@binkert.org << "Total Number Demand : " << total_demand << endl 2067039Snate@binkert.org << "Total Number Prefetches : " << m_outstanding_count - total_demand 2077039Snate@binkert.org << endl << endl << endl; 2087039Snate@binkert.org#endif 2096145Snate@binkert.org} 2106145Snate@binkert.org 2116145Snate@binkert.org// Insert the request on the correct request table. Return true if 2126145Snate@binkert.org// the entry was already present. 2138615Snilay@cs.wisc.eduRequestStatus 2148615Snilay@cs.wisc.eduSequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 2157039Snate@binkert.org{ 2168641Snate@binkert.org assert(m_outstanding_count == 2178641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2186145Snate@binkert.org 2197039Snate@binkert.org // See if we should schedule a deadlock check 2209342SAndreas.Sandberg@arm.com if (!deadlockCheckEvent.scheduled() && 22110913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) { 2229465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 2237039Snate@binkert.org } 2246145Snate@binkert.org 22511025Snilay@cs.wisc.edu Addr line_addr = makeLineAddress(pkt->getAddr()); 2269224Sandreas.hansson@arm.com // Create a default entry, mapping the address to NULL, the cast is 2279224Sandreas.hansson@arm.com // there to make gcc 4.4 happy 2289224Sandreas.hansson@arm.com RequestTable::value_type default_entry(line_addr, 2299224Sandreas.hansson@arm.com (SequencerRequest*) NULL); 2309224Sandreas.hansson@arm.com 2318615Snilay@cs.wisc.edu if ((request_type == RubyRequestType_ST) || 2328615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Read) || 2338615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Write) || 2348615Snilay@cs.wisc.edu (request_type == RubyRequestType_Load_Linked) || 2358615Snilay@cs.wisc.edu (request_type == RubyRequestType_Store_Conditional) || 2368615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Read) || 2378615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Write) || 2388615Snilay@cs.wisc.edu (request_type == RubyRequestType_FLUSH)) { 2398615Snilay@cs.wisc.edu 2408615Snilay@cs.wisc.edu // Check if there is any outstanding read request for the same 2418615Snilay@cs.wisc.edu // cache line. 2428615Snilay@cs.wisc.edu if (m_readRequestTable.count(line_addr) > 0) { 24310012Snilay@cs.wisc.edu m_store_waiting_on_load++; 2448615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2458615Snilay@cs.wisc.edu } 2468615Snilay@cs.wisc.edu 2477455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2489224Sandreas.hansson@arm.com m_writeRequestTable.insert(default_entry); 2498615Snilay@cs.wisc.edu if (r.second) { 2508615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2519465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2528615Snilay@cs.wisc.edu m_outstanding_count++; 2538615Snilay@cs.wisc.edu } else { 2548615Snilay@cs.wisc.edu // There is an outstanding write request for the cache line 25510012Snilay@cs.wisc.edu m_store_waiting_on_store++; 2568615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2578615Snilay@cs.wisc.edu } 2588615Snilay@cs.wisc.edu } else { 2598615Snilay@cs.wisc.edu // Check if there is any outstanding write request for the same 2608615Snilay@cs.wisc.edu // cache line. 2618615Snilay@cs.wisc.edu if (m_writeRequestTable.count(line_addr) > 0) { 26210012Snilay@cs.wisc.edu m_load_waiting_on_store++; 2638615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2648615Snilay@cs.wisc.edu } 2657039Snate@binkert.org 2667455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2679224Sandreas.hansson@arm.com m_readRequestTable.insert(default_entry); 2687039Snate@binkert.org 2698615Snilay@cs.wisc.edu if (r.second) { 2708615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2719465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2728615Snilay@cs.wisc.edu m_outstanding_count++; 2738615Snilay@cs.wisc.edu } else { 2748615Snilay@cs.wisc.edu // There is an outstanding read request for the cache line 27510012Snilay@cs.wisc.edu m_load_waiting_on_load++; 2768615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2777039Snate@binkert.org } 2786145Snate@binkert.org } 2796145Snate@binkert.org 28010012Snilay@cs.wisc.edu m_outstandReqHist.sample(m_outstanding_count); 2818641Snate@binkert.org assert(m_outstanding_count == 2828641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2836145Snate@binkert.org 2848615Snilay@cs.wisc.edu return RequestStatus_Ready; 2856145Snate@binkert.org} 2866145Snate@binkert.org 2877039Snate@binkert.orgvoid 2887455Snate@binkert.orgSequencer::markRemoved() 2897455Snate@binkert.org{ 2907455Snate@binkert.org m_outstanding_count--; 2917455Snate@binkert.org assert(m_outstanding_count == 2927455Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 2937455Snate@binkert.org} 2947455Snate@binkert.org 2957455Snate@binkert.orgvoid 2967039Snate@binkert.orgSequencer::removeRequest(SequencerRequest* srequest) 2977039Snate@binkert.org{ 2987039Snate@binkert.org assert(m_outstanding_count == 2997039Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 3006145Snate@binkert.org 30111025Snilay@cs.wisc.edu Addr line_addr = makeLineAddress(srequest->pkt->getAddr()); 3028615Snilay@cs.wisc.edu if ((srequest->m_type == RubyRequestType_ST) || 3038615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_RMW_Read) || 3048615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_RMW_Write) || 3058615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Load_Linked) || 3068615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Store_Conditional) || 3078615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Locked_RMW_Read) || 3088615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { 3097455Snate@binkert.org m_writeRequestTable.erase(line_addr); 3107039Snate@binkert.org } else { 3117455Snate@binkert.org m_readRequestTable.erase(line_addr); 3127039Snate@binkert.org } 3136285Snate@binkert.org 3147455Snate@binkert.org markRemoved(); 3156145Snate@binkert.org} 3166145Snate@binkert.org 3179563Sgope@wisc.eduvoid 31811025Snilay@cs.wisc.eduSequencer::invalidateSC(Addr address) 3199563Sgope@wisc.edu{ 32011049Snilay@cs.wisc.edu RequestTable::iterator i = m_writeRequestTable.find(address); 32111049Snilay@cs.wisc.edu if (i != m_writeRequestTable.end()) { 32211049Snilay@cs.wisc.edu SequencerRequest* request = i->second; 32311049Snilay@cs.wisc.edu // The controller has lost the coherence permissions, hence the lock 32411049Snilay@cs.wisc.edu // on the cache line maintained by the cache should be cleared. 32511049Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 32611049Snilay@cs.wisc.edu m_dataCache_ptr->clearLocked(address); 32711049Snilay@cs.wisc.edu } 3289563Sgope@wisc.edu } 3299563Sgope@wisc.edu} 3309563Sgope@wisc.edu 3317560SBrad.Beckmann@amd.combool 33211025Snilay@cs.wisc.eduSequencer::handleLlsc(Addr address, SequencerRequest* request) 3337550SBrad.Beckmann@amd.com{ 33411049Snilay@cs.wisc.edu // 3357560SBrad.Beckmann@amd.com // The success flag indicates whether the LLSC operation was successful. 3367560SBrad.Beckmann@amd.com // LL ops will always succeed, but SC may fail if the cache line is no 3377560SBrad.Beckmann@amd.com // longer locked. 33811049Snilay@cs.wisc.edu // 3397560SBrad.Beckmann@amd.com bool success = true; 3408615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 34111049Snilay@cs.wisc.edu if (!m_dataCache_ptr->isLocked(address, m_version)) { 3427550SBrad.Beckmann@amd.com // 3437550SBrad.Beckmann@amd.com // For failed SC requests, indicate the failure to the cpu by 3447550SBrad.Beckmann@amd.com // setting the extra data to zero. 3457550SBrad.Beckmann@amd.com // 3468615Snilay@cs.wisc.edu request->pkt->req->setExtraData(0); 3477560SBrad.Beckmann@amd.com success = false; 3487550SBrad.Beckmann@amd.com } else { 3497550SBrad.Beckmann@amd.com // 3507550SBrad.Beckmann@amd.com // For successful SC requests, indicate the success to the cpu by 35110917Sbrandon.potter@amd.com // setting the extra data to one. 3527550SBrad.Beckmann@amd.com // 3538615Snilay@cs.wisc.edu request->pkt->req->setExtraData(1); 3547550SBrad.Beckmann@amd.com } 3557560SBrad.Beckmann@amd.com // 3567560SBrad.Beckmann@amd.com // Independent of success, all SC operations must clear the lock 3577560SBrad.Beckmann@amd.com // 35811049Snilay@cs.wisc.edu m_dataCache_ptr->clearLocked(address); 3598615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Load_Linked) { 3607550SBrad.Beckmann@amd.com // 3617550SBrad.Beckmann@amd.com // Note: To fully follow Alpha LLSC semantics, should the LL clear any 3627550SBrad.Beckmann@amd.com // previously locked cache lines? 3637550SBrad.Beckmann@amd.com // 36411049Snilay@cs.wisc.edu m_dataCache_ptr->setLocked(address, m_version); 36511049Snilay@cs.wisc.edu } else if ((m_dataCache_ptr->isTagPresent(address)) && 36611049Snilay@cs.wisc.edu (m_dataCache_ptr->isLocked(address, m_version))) { 3677550SBrad.Beckmann@amd.com // 3687550SBrad.Beckmann@amd.com // Normal writes should clear the locked address 3697550SBrad.Beckmann@amd.com // 37011049Snilay@cs.wisc.edu m_dataCache_ptr->clearLocked(address); 3717550SBrad.Beckmann@amd.com } 3727560SBrad.Beckmann@amd.com return success; 3737550SBrad.Beckmann@amd.com} 3747550SBrad.Beckmann@amd.com 3757550SBrad.Beckmann@amd.comvoid 3769773Snilay@cs.wisc.eduSequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 3779773Snilay@cs.wisc.edu const MachineType respondingMach, 3789773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 3799773Snilay@cs.wisc.edu Cycles initialRequestTime, 3809773Snilay@cs.wisc.edu Cycles forwardRequestTime, 3819773Snilay@cs.wisc.edu Cycles firstResponseTime, Cycles completionTime) 3827039Snate@binkert.org{ 38310012Snilay@cs.wisc.edu m_latencyHist.sample(cycles); 38410012Snilay@cs.wisc.edu m_typeLatencyHist[type]->sample(cycles); 3859773Snilay@cs.wisc.edu 3869773Snilay@cs.wisc.edu if (isExternalHit) { 38710012Snilay@cs.wisc.edu m_missLatencyHist.sample(cycles); 38810012Snilay@cs.wisc.edu m_missTypeLatencyHist[type]->sample(cycles); 3899773Snilay@cs.wisc.edu 3909773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 39110012Snilay@cs.wisc.edu m_missMachLatencyHist[respondingMach]->sample(cycles); 39210012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3939773Snilay@cs.wisc.edu 3949773Snilay@cs.wisc.edu if ((issuedTime <= initialRequestTime) && 3959773Snilay@cs.wisc.edu (initialRequestTime <= forwardRequestTime) && 3969773Snilay@cs.wisc.edu (forwardRequestTime <= firstResponseTime) && 3979773Snilay@cs.wisc.edu (firstResponseTime <= completionTime)) { 3989773Snilay@cs.wisc.edu 39910012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[respondingMach]->sample( 4009773Snilay@cs.wisc.edu initialRequestTime - issuedTime); 40110012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[respondingMach]->sample( 4029773Snilay@cs.wisc.edu forwardRequestTime - initialRequestTime); 40310012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 4049773Snilay@cs.wisc.edu firstResponseTime - forwardRequestTime); 40510012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 4069773Snilay@cs.wisc.edu completionTime - firstResponseTime); 4079773Snilay@cs.wisc.edu } else { 4089773Snilay@cs.wisc.edu m_IncompleteTimes[respondingMach]++; 4099773Snilay@cs.wisc.edu } 4109773Snilay@cs.wisc.edu } 4119773Snilay@cs.wisc.edu } else { 41210012Snilay@cs.wisc.edu m_hitLatencyHist.sample(cycles); 41310012Snilay@cs.wisc.edu m_hitTypeLatencyHist[type]->sample(cycles); 4149773Snilay@cs.wisc.edu 4159773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 41610012Snilay@cs.wisc.edu m_hitMachLatencyHist[respondingMach]->sample(cycles); 41710012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 4189773Snilay@cs.wisc.edu } 4199773Snilay@cs.wisc.edu } 4207546SBrad.Beckmann@amd.com} 4217546SBrad.Beckmann@amd.com 4227546SBrad.Beckmann@amd.comvoid 42311025Snilay@cs.wisc.eduSequencer::writeCallback(Addr address, DataBlock& data, 4249773Snilay@cs.wisc.edu const bool externalHit, const MachineType mach, 4259773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4269773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4279773Snilay@cs.wisc.edu const Cycles firstResponseTime) 4287565SBrad.Beckmann@amd.com{ 42911025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 43011025Snilay@cs.wisc.edu assert(m_writeRequestTable.count(makeLineAddress(address))); 4316145Snate@binkert.org 4327455Snate@binkert.org RequestTable::iterator i = m_writeRequestTable.find(address); 4337455Snate@binkert.org assert(i != m_writeRequestTable.end()); 4347455Snate@binkert.org SequencerRequest* request = i->second; 4356145Snate@binkert.org 4367455Snate@binkert.org m_writeRequestTable.erase(i); 4377455Snate@binkert.org markRemoved(); 4386846Spdudnik@cs.wisc.edu 4398615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_ST) || 4408615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_ATOMIC) || 4418615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Read) || 4428615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Write) || 4438615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Load_Linked) || 4448615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Store_Conditional) || 4458615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Read) || 4468615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Write) || 4478615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_FLUSH)); 4488184Ssomayeh@cs.wisc.edu 4497550SBrad.Beckmann@amd.com // 4507550SBrad.Beckmann@amd.com // For Alpha, properly handle LL, SC, and write requests with respect to 4517550SBrad.Beckmann@amd.com // locked cache blocks. 4527550SBrad.Beckmann@amd.com // 4538171Stushar@csail.mit.edu // Not valid for Network_test protocl 4548171Stushar@csail.mit.edu // 4558171Stushar@csail.mit.edu bool success = true; 4568171Stushar@csail.mit.edu if(!m_usingNetworkTester) 4578171Stushar@csail.mit.edu success = handleLlsc(address, request); 4587550SBrad.Beckmann@amd.com 4598615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Locked_RMW_Read) { 4607039Snate@binkert.org m_controller->blockOnQueue(address, m_mandatory_q_ptr); 4618615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 4627039Snate@binkert.org m_controller->unblock(address); 4637039Snate@binkert.org } 4646863Sdrh5@cs.wisc.edu 4659773Snilay@cs.wisc.edu hitCallback(request, data, success, mach, externalHit, 4667565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4676145Snate@binkert.org} 4686145Snate@binkert.org 4697039Snate@binkert.orgvoid 47011025Snilay@cs.wisc.eduSequencer::readCallback(Addr address, DataBlock& data, 4719773Snilay@cs.wisc.edu bool externalHit, const MachineType mach, 4729507Snilay@cs.wisc.edu Cycles initialRequestTime, 4739507Snilay@cs.wisc.edu Cycles forwardRequestTime, 4749507Snilay@cs.wisc.edu Cycles firstResponseTime) 4757565SBrad.Beckmann@amd.com{ 47611025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 47711025Snilay@cs.wisc.edu assert(m_readRequestTable.count(makeLineAddress(address))); 4786145Snate@binkert.org 4797455Snate@binkert.org RequestTable::iterator i = m_readRequestTable.find(address); 4807455Snate@binkert.org assert(i != m_readRequestTable.end()); 4817455Snate@binkert.org SequencerRequest* request = i->second; 4827455Snate@binkert.org 4837455Snate@binkert.org m_readRequestTable.erase(i); 4847455Snate@binkert.org markRemoved(); 4856145Snate@binkert.org 4868615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_LD) || 4878615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_IFETCH)); 4886285Snate@binkert.org 4899773Snilay@cs.wisc.edu hitCallback(request, data, true, mach, externalHit, 4907565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4916145Snate@binkert.org} 4926145Snate@binkert.org 4937039Snate@binkert.orgvoid 4949773Snilay@cs.wisc.eduSequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 4959773Snilay@cs.wisc.edu bool llscSuccess, 4969773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 4979773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4989773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4999773Snilay@cs.wisc.edu const Cycles firstResponseTime) 5007039Snate@binkert.org{ 5018615Snilay@cs.wisc.edu PacketPtr pkt = srequest->pkt; 50211025Snilay@cs.wisc.edu Addr request_address(pkt->getAddr()); 50311049Snilay@cs.wisc.edu Addr request_line_address = makeLineAddress(pkt->getAddr()); 5048615Snilay@cs.wisc.edu RubyRequestType type = srequest->m_type; 5059507Snilay@cs.wisc.edu Cycles issued_time = srequest->issue_time; 5066145Snate@binkert.org 50711049Snilay@cs.wisc.edu // Set this cache entry to the most recently used 50811049Snilay@cs.wisc.edu if (type == RubyRequestType_IFETCH) { 50911049Snilay@cs.wisc.edu m_instCache_ptr->setMRU(request_line_address); 51011049Snilay@cs.wisc.edu } else { 51111049Snilay@cs.wisc.edu m_dataCache_ptr->setMRU(request_line_address); 51211049Snilay@cs.wisc.edu } 51311049Snilay@cs.wisc.edu 5149465Snilay@cs.wisc.edu assert(curCycle() >= issued_time); 5159773Snilay@cs.wisc.edu Cycles total_latency = curCycle() - issued_time; 5166145Snate@binkert.org 5179773Snilay@cs.wisc.edu // Profile the latency for all demand accesses. 5189773Snilay@cs.wisc.edu recordMissLatency(total_latency, type, mach, externalHit, issued_time, 5199773Snilay@cs.wisc.edu initialRequestTime, forwardRequestTime, 5209773Snilay@cs.wisc.edu firstResponseTime, curCycle()); 5216285Snate@binkert.org 52211025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", 5239773Snilay@cs.wisc.edu curTick(), m_version, "Seq", 5249773Snilay@cs.wisc.edu llscSuccess ? "Done" : "SC_Failed", "", "", 5259773Snilay@cs.wisc.edu request_address, total_latency); 5266285Snate@binkert.org 52710562Sandreas.hansson@arm.com // update the data unless it is a non-data-carrying flush 52810837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 52910563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 53011025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 53110562Sandreas.hansson@arm.com } else if (!pkt->isFlush()) { 5327039Snate@binkert.org if ((type == RubyRequestType_LD) || 5337039Snate@binkert.org (type == RubyRequestType_IFETCH) || 5347039Snate@binkert.org (type == RubyRequestType_RMW_Read) || 5357908Shestness@cs.utexas.edu (type == RubyRequestType_Locked_RMW_Read) || 5367907Shestness@cs.utexas.edu (type == RubyRequestType_Load_Linked)) { 53710562Sandreas.hansson@arm.com memcpy(pkt->getPtr<uint8_t>(), 53811025Snilay@cs.wisc.edu data.getData(getOffset(request_address), pkt->getSize()), 5398615Snilay@cs.wisc.edu pkt->getSize()); 54010954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "read data %s\n", data); 5417039Snate@binkert.org } else { 54210563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 54311025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 54410954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "set data %s\n", data); 5457039Snate@binkert.org } 5467039Snate@binkert.org } 5477023SBrad.Beckmann@amd.com 5487039Snate@binkert.org // If using the RubyTester, update the RubyTester sender state's 5497039Snate@binkert.org // subBlock with the recieved data. The tester will later access 5507039Snate@binkert.org // this state. 5517039Snate@binkert.org if (m_usingRubyTester) { 55210657Sandreas.hansson@arm.com DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n", 55310657Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 5547039Snate@binkert.org RubyTester::SenderState* testerSenderState = 55510089Sandreas.hansson@arm.com pkt->findNextSenderState<RubyTester::SenderState>(); 55610089Sandreas.hansson@arm.com assert(testerSenderState); 5579542Sandreas.hansson@arm.com testerSenderState->subBlock.mergeFrom(data); 5587039Snate@binkert.org } 5597023SBrad.Beckmann@amd.com 5607039Snate@binkert.org delete srequest; 5618688Snilay@cs.wisc.edu 56210919Sbrandon.potter@amd.com RubySystem *rs = m_ruby_system; 56310837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 5649632Sjthestness@gmail.com assert(pkt->req); 5659632Sjthestness@gmail.com delete pkt->req; 5668688Snilay@cs.wisc.edu delete pkt; 56710919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFetchRequest(); 56810837Sjthestness@gmail.com } else if (RubySystem::getCooldownEnabled()) { 5698688Snilay@cs.wisc.edu delete pkt; 57010919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFlushRequest(); 5718688Snilay@cs.wisc.edu } else { 5728688Snilay@cs.wisc.edu ruby_hit_callback(pkt); 5738688Snilay@cs.wisc.edu } 5746285Snate@binkert.org} 5756285Snate@binkert.org 5767039Snate@binkert.orgbool 5777039Snate@binkert.orgSequencer::empty() const 5787039Snate@binkert.org{ 5797455Snate@binkert.org return m_writeRequestTable.empty() && m_readRequestTable.empty(); 5806145Snate@binkert.org} 5816145Snate@binkert.org 5827039Snate@binkert.orgRequestStatus 5838615Snilay@cs.wisc.eduSequencer::makeRequest(PacketPtr pkt) 5847039Snate@binkert.org{ 5858615Snilay@cs.wisc.edu if (m_outstanding_count >= m_max_outstanding_requests) { 5868615Snilay@cs.wisc.edu return RequestStatus_BufferFull; 5878615Snilay@cs.wisc.edu } 5888615Snilay@cs.wisc.edu 5898615Snilay@cs.wisc.edu RubyRequestType primary_type = RubyRequestType_NULL; 5908615Snilay@cs.wisc.edu RubyRequestType secondary_type = RubyRequestType_NULL; 5918615Snilay@cs.wisc.edu 5928615Snilay@cs.wisc.edu if (pkt->isLLSC()) { 5938615Snilay@cs.wisc.edu // 5948615Snilay@cs.wisc.edu // Alpha LL/SC instructions need to be handled carefully by the cache 5958615Snilay@cs.wisc.edu // coherence protocol to ensure they follow the proper semantics. In 5968615Snilay@cs.wisc.edu // particular, by identifying the operations as atomic, the protocol 5978615Snilay@cs.wisc.edu // should understand that migratory sharing optimizations should not 5988615Snilay@cs.wisc.edu // be performed (i.e. a load between the LL and SC should not steal 5998615Snilay@cs.wisc.edu // away exclusive permission). 6008615Snilay@cs.wisc.edu // 6018615Snilay@cs.wisc.edu if (pkt->isWrite()) { 6028615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing SC\n"); 6038615Snilay@cs.wisc.edu primary_type = RubyRequestType_Store_Conditional; 6048615Snilay@cs.wisc.edu } else { 6058615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing LL\n"); 6068615Snilay@cs.wisc.edu assert(pkt->isRead()); 6078615Snilay@cs.wisc.edu primary_type = RubyRequestType_Load_Linked; 6088615Snilay@cs.wisc.edu } 6098615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ATOMIC; 61010760Ssteve.reinhardt@amd.com } else if (pkt->req->isLockedRMW()) { 6118615Snilay@cs.wisc.edu // 6128615Snilay@cs.wisc.edu // x86 locked instructions are translated to store cache coherence 6138615Snilay@cs.wisc.edu // requests because these requests should always be treated as read 6148615Snilay@cs.wisc.edu // exclusive operations and should leverage any migratory sharing 6158615Snilay@cs.wisc.edu // optimization built into the protocol. 6168615Snilay@cs.wisc.edu // 6178615Snilay@cs.wisc.edu if (pkt->isWrite()) { 6188615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 6198615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Write; 6208615Snilay@cs.wisc.edu } else { 6218615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 6228615Snilay@cs.wisc.edu assert(pkt->isRead()); 6238615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Read; 6248615Snilay@cs.wisc.edu } 6258615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 6268615Snilay@cs.wisc.edu } else { 6278615Snilay@cs.wisc.edu if (pkt->isRead()) { 6288615Snilay@cs.wisc.edu if (pkt->req->isInstFetch()) { 6298615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_IFETCH; 6308615Snilay@cs.wisc.edu } else { 6318615Snilay@cs.wisc.edu bool storeCheck = false; 63210467Sandreas.hansson@arm.com // only X86 need the store check 63310467Sandreas.hansson@arm.com if (system->getArch() == Arch::X86ISA) { 63410467Sandreas.hansson@arm.com uint32_t flags = pkt->req->getFlags(); 63510467Sandreas.hansson@arm.com storeCheck = flags & 63610467Sandreas.hansson@arm.com (X86ISA::StoreCheck << X86ISA::FlagShift); 63710467Sandreas.hansson@arm.com } 6388615Snilay@cs.wisc.edu if (storeCheck) { 6398615Snilay@cs.wisc.edu primary_type = RubyRequestType_RMW_Read; 6408615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 6418615Snilay@cs.wisc.edu } else { 6428615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_LD; 6438615Snilay@cs.wisc.edu } 6448615Snilay@cs.wisc.edu } 6458615Snilay@cs.wisc.edu } else if (pkt->isWrite()) { 6468615Snilay@cs.wisc.edu // 6478615Snilay@cs.wisc.edu // Note: M5 packets do not differentiate ST from RMW_Write 6488615Snilay@cs.wisc.edu // 6498615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_ST; 6508615Snilay@cs.wisc.edu } else if (pkt->isFlush()) { 6518615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_FLUSH; 6528615Snilay@cs.wisc.edu } else { 6538615Snilay@cs.wisc.edu panic("Unsupported ruby packet type\n"); 6548615Snilay@cs.wisc.edu } 6558615Snilay@cs.wisc.edu } 6568615Snilay@cs.wisc.edu 6578615Snilay@cs.wisc.edu RequestStatus status = insertRequest(pkt, primary_type); 6587039Snate@binkert.org if (status != RequestStatus_Ready) 6597039Snate@binkert.org return status; 6606349Spdudnik@gmail.com 6618615Snilay@cs.wisc.edu issueRequest(pkt, secondary_type); 6626145Snate@binkert.org 6637039Snate@binkert.org // TODO: issue hardware prefetches here 6647039Snate@binkert.org return RequestStatus_Issued; 6656145Snate@binkert.org} 6666145Snate@binkert.org 6677039Snate@binkert.orgvoid 6688615Snilay@cs.wisc.eduSequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 6697039Snate@binkert.org{ 6709216Sandreas.hansson@arm.com assert(pkt != NULL); 67111005Sandreas.sandberg@arm.com ContextID proc_id = pkt->req->hasContextId() ? 67211005Sandreas.sandberg@arm.com pkt->req->contextId() : InvalidContextID; 6736285Snate@binkert.org 6748615Snilay@cs.wisc.edu // If valid, copy the pc to the ruby request 6758615Snilay@cs.wisc.edu Addr pc = 0; 6768615Snilay@cs.wisc.edu if (pkt->req->hasPC()) { 6778615Snilay@cs.wisc.edu pc = pkt->req->getPC(); 6787039Snate@binkert.org } 6796285Snate@binkert.org 68010562Sandreas.hansson@arm.com // check if the packet has data as for example prefetch and flush 68110562Sandreas.hansson@arm.com // requests do not 68210472Sandreas.hansson@arm.com std::shared_ptr<RubyRequest> msg = 68310472Sandreas.hansson@arm.com std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(), 68410562Sandreas.hansson@arm.com pkt->isFlush() ? 68510562Sandreas.hansson@arm.com nullptr : pkt->getPtr<uint8_t>(), 68610472Sandreas.hansson@arm.com pkt->getSize(), pc, secondary_type, 68710472Sandreas.hansson@arm.com RubyAccessMode_Supervisor, pkt, 68810472Sandreas.hansson@arm.com PrefetchBit_No, proc_id); 6896285Snate@binkert.org 69011025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", 6918266Sksewell@umich.edu curTick(), m_version, "Seq", "Begin", "", "", 6928615Snilay@cs.wisc.edu msg->getPhysicalAddress(), 6938615Snilay@cs.wisc.edu RubyRequestType_to_string(secondary_type)); 6946285Snate@binkert.org 69511019Sjthestness@gmail.com // The Sequencer currently assesses instruction and data cache hit latency 69611019Sjthestness@gmail.com // for the top-level caches at the beginning of a memory access. 69711019Sjthestness@gmail.com // TODO: Eventually, this latency should be moved to represent the actual 69811019Sjthestness@gmail.com // cache access latency portion of the memory access. This will require 69911019Sjthestness@gmail.com // changing cache controller protocol files to assess the latency on the 70011019Sjthestness@gmail.com // access response path. 70111019Sjthestness@gmail.com Cycles latency(0); // Initialize to zero to catch misconfigured latency 7028615Snilay@cs.wisc.edu if (secondary_type == RubyRequestType_IFETCH) 70311019Sjthestness@gmail.com latency = m_inst_cache_hit_latency; 7047039Snate@binkert.org else 70511019Sjthestness@gmail.com latency = m_data_cache_hit_latency; 7066285Snate@binkert.org 7077039Snate@binkert.org // Send the message to the cache controller 7087039Snate@binkert.org assert(latency > 0); 7096145Snate@binkert.org 7107039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 7117039Snate@binkert.org m_mandatory_q_ptr->enqueue(msg, latency); 7126145Snate@binkert.org} 7136145Snate@binkert.org 7147455Snate@binkert.orgtemplate <class KEY, class VALUE> 7157455Snate@binkert.orgstd::ostream & 7167455Snate@binkert.orgoperator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 7177455Snate@binkert.org{ 7187455Snate@binkert.org typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 7197455Snate@binkert.org typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 7207455Snate@binkert.org 7217455Snate@binkert.org out << "["; 7227455Snate@binkert.org for (; i != end; ++i) 7237455Snate@binkert.org out << " " << i->first << "=" << i->second; 7247455Snate@binkert.org out << " ]"; 7257455Snate@binkert.org 7267455Snate@binkert.org return out; 7277455Snate@binkert.org} 7287455Snate@binkert.org 7297039Snate@binkert.orgvoid 7307039Snate@binkert.orgSequencer::print(ostream& out) const 7317039Snate@binkert.org{ 7327039Snate@binkert.org out << "[Sequencer: " << m_version 7337039Snate@binkert.org << ", outstanding requests: " << m_outstanding_count 7347039Snate@binkert.org << ", read request table: " << m_readRequestTable 7357039Snate@binkert.org << ", write request table: " << m_writeRequestTable 7367039Snate@binkert.org << "]"; 7377039Snate@binkert.org} 7387039Snate@binkert.org 7397039Snate@binkert.org// this can be called from setState whenever coherence permissions are 7407039Snate@binkert.org// upgraded when invoked, coherence violations will be checked for the 7417039Snate@binkert.org// given block 7427039Snate@binkert.orgvoid 74311025Snilay@cs.wisc.eduSequencer::checkCoherence(Addr addr) 7447039Snate@binkert.org{ 7456145Snate@binkert.org#ifdef CHECK_COHERENCE 74610919Sbrandon.potter@amd.com m_ruby_system->checkGlobalCoherenceInvariant(addr); 7476145Snate@binkert.org#endif 7486145Snate@binkert.org} 7498717Snilay@cs.wisc.edu 7508717Snilay@cs.wisc.eduvoid 7519104Shestness@cs.utexas.eduSequencer::recordRequestType(SequencerRequestType requestType) { 7529104Shestness@cs.utexas.edu DPRINTF(RubyStats, "Recorded statistic: %s\n", 7539104Shestness@cs.utexas.edu SequencerRequestType_to_string(requestType)); 7549104Shestness@cs.utexas.edu} 7559104Shestness@cs.utexas.edu 7569104Shestness@cs.utexas.edu 7579104Shestness@cs.utexas.eduvoid 75811025Snilay@cs.wisc.eduSequencer::evictionCallback(Addr address) 7598717Snilay@cs.wisc.edu{ 7608717Snilay@cs.wisc.edu ruby_eviction_callback(address); 7618717Snilay@cs.wisc.edu} 76210012Snilay@cs.wisc.edu 76310012Snilay@cs.wisc.eduvoid 76410012Snilay@cs.wisc.eduSequencer::regStats() 76510012Snilay@cs.wisc.edu{ 76610012Snilay@cs.wisc.edu m_store_waiting_on_load 76710012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_load") 76810012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending load") 76910012Snilay@cs.wisc.edu .flags(Stats::nozero); 77010012Snilay@cs.wisc.edu m_store_waiting_on_store 77110012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_store") 77210012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending store") 77310012Snilay@cs.wisc.edu .flags(Stats::nozero); 77410012Snilay@cs.wisc.edu m_load_waiting_on_load 77510012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_load") 77610012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending load") 77710012Snilay@cs.wisc.edu .flags(Stats::nozero); 77810012Snilay@cs.wisc.edu m_load_waiting_on_store 77910012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_store") 78010012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending store") 78110012Snilay@cs.wisc.edu .flags(Stats::nozero); 78210012Snilay@cs.wisc.edu 78310012Snilay@cs.wisc.edu // These statistical variables are not for display. 78410012Snilay@cs.wisc.edu // The profiler will collate these across different 78510012Snilay@cs.wisc.edu // sequencers and display those collated statistics. 78610012Snilay@cs.wisc.edu m_outstandReqHist.init(10); 78710012Snilay@cs.wisc.edu m_latencyHist.init(10); 78810012Snilay@cs.wisc.edu m_hitLatencyHist.init(10); 78910012Snilay@cs.wisc.edu m_missLatencyHist.init(10); 79010012Snilay@cs.wisc.edu 79110012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 79210012Snilay@cs.wisc.edu m_typeLatencyHist.push_back(new Stats::Histogram()); 79310012Snilay@cs.wisc.edu m_typeLatencyHist[i]->init(10); 79410012Snilay@cs.wisc.edu 79510012Snilay@cs.wisc.edu m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 79610012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->init(10); 79710012Snilay@cs.wisc.edu 79810012Snilay@cs.wisc.edu m_missTypeLatencyHist.push_back(new Stats::Histogram()); 79910012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->init(10); 80010012Snilay@cs.wisc.edu } 80110012Snilay@cs.wisc.edu 80210012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 80310012Snilay@cs.wisc.edu m_hitMachLatencyHist.push_back(new Stats::Histogram()); 80410012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->init(10); 80510012Snilay@cs.wisc.edu 80610012Snilay@cs.wisc.edu m_missMachLatencyHist.push_back(new Stats::Histogram()); 80710012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->init(10); 80810012Snilay@cs.wisc.edu 80910012Snilay@cs.wisc.edu m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 81010012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->init(10); 81110012Snilay@cs.wisc.edu 81210012Snilay@cs.wisc.edu m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 81310012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->init(10); 81410012Snilay@cs.wisc.edu 81510012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 81610012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->init(10); 81710012Snilay@cs.wisc.edu 81810012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 81910012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->init(10); 82010012Snilay@cs.wisc.edu } 82110012Snilay@cs.wisc.edu 82210012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 82310012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 82410012Snilay@cs.wisc.edu m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 82510012Snilay@cs.wisc.edu 82610012Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 82710012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 82810012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->init(10); 82910012Snilay@cs.wisc.edu 83010012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 83110012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->init(10); 83210012Snilay@cs.wisc.edu } 83310012Snilay@cs.wisc.edu } 83410012Snilay@cs.wisc.edu} 835