SConscript revision 8492
110206Sandreas.hansson@arm.com# -*- mode:python -*- 29243SN/A 39243SN/A# Copyright (c) 2009 The Hewlett-Packard Development Company 49243SN/A# All rights reserved. 59243SN/A# 69243SN/A# Redistribution and use in source and binary forms, with or without 79243SN/A# modification, are permitted provided that the following conditions are 89243SN/A# met: redistributions of source code must retain the above copyright 99243SN/A# notice, this list of conditions and the following disclaimer; 109243SN/A# redistributions in binary form must reproduce the above copyright 119243SN/A# notice, this list of conditions and the following disclaimer in the 129243SN/A# documentation and/or other materials provided with the distribution; 139831SN/A# neither the name of the copyright holders nor the names of its 149831SN/A# contributors may be used to endorse or promote products derived from 159831SN/A# this software without specific prior written permission. 169243SN/A# 179243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 189243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 199243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 209243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 219243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 229243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 239243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 249243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 259243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 269243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 279243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 289243SN/A# 299243SN/A# Authors: Nathan Binkert 309243SN/A 319243SN/AImport('*') 329243SN/A 339243SN/Aif env['PROTOCOL'] == 'None': 349243SN/A Return() 359243SN/A 369243SN/ASimObject('Cache.py') 379243SN/ASimObject('Sequencer.py') 389243SN/ASimObject('DirectoryMemory.py') 399243SN/ASimObject('MemoryControl.py') 409243SN/ASimObject('WireBuffer.py') 419243SN/ASimObject('RubySystem.py') 429243SN/A 439243SN/ASource('DMASequencer.cc') 449243SN/ASource('DirectoryMemory.cc') 459243SN/ASource('SparseMemory.cc') 469243SN/ASource('CacheMemory.cc') 479243SN/ASource('MemoryControl.cc') 489243SN/ASource('WireBuffer.cc') 4910136SN/ASource('MemoryNode.cc') 5010136SN/ASource('PersistentTable.cc') 5110136SN/ASource('RubyPort.cc') 5210136SN/ASource('Sequencer.cc', Werror=False) 5310136SN/ASource('System.cc') 5410136SN/ASource('TimerTable.cc') 5510136SN/A