RubySystem.hh revision 6876
12330SN/A 22330SN/A/* 32330SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 42330SN/A * All rights reserved. 52330SN/A * 62330SN/A * Redistribution and use in source and binary forms, with or without 72330SN/A * modification, are permitted provided that the following conditions are 82330SN/A * met: redistributions of source code must retain the above copyright 92330SN/A * notice, this list of conditions and the following disclaimer; 102330SN/A * redistributions in binary form must reproduce the above copyright 112330SN/A * notice, this list of conditions and the following disclaimer in the 122330SN/A * documentation and/or other materials provided with the distribution; 132330SN/A * neither the name of the copyright holders nor the names of its 142330SN/A * contributors may be used to endorse or promote products derived from 152330SN/A * this software without specific prior written permission. 162330SN/A * 172330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282689Sktlim@umich.edu */ 292330SN/A 302292SN/A/* 312292SN/A * System.hh 322292SN/A * 332292SN/A * Description: Contains all of the various parts of the system we are 342980Sgblack@eecs.umich.edu * simulating. Performs allocation, deallocation, and setup of all 352362SN/A * the major components of the system 362680Sktlim@umich.edu * 372292SN/A * $Id$ 382678Sktlim@umich.edu * 392683Sktlim@umich.edu */ 402678Sktlim@umich.edu 412683Sktlim@umich.edu#ifndef SYSTEM_H 422678Sktlim@umich.edu#define SYSTEM_H 432678Sktlim@umich.edu 442292SN/A#include "mem/ruby/system/RubyPort.hh" 452292SN/A#include "mem/ruby/common/Global.hh" 462292SN/A#include "mem/gems_common/Vector.hh" 472292SN/A#include "mem/ruby/eventqueue/RubyEventQueue.hh" 482330SN/A#include <map> 492330SN/A#include "sim/sim_object.hh" 502330SN/A#include "params/RubySystem.hh" 512292SN/A 522292SN/Aclass Profiler; 532862Sktlim@umich.educlass Network; 542862Sktlim@umich.educlass CacheRecorder; 552330SN/Aclass Tracer; 562330SN/Aclass Sequencer; 572330SN/Aclass DMASequencer; 582330SN/Aclass MemoryVector; 592330SN/Aclass AbstractController; 602330SN/Aclass MessageBuffer; 612292SN/Aclass CacheMemory; 622683Sktlim@umich.educlass DirectoryMemory; 632683Sktlim@umich.educlass Topology; 642292SN/Aclass MemoryControl; 652683Sktlim@umich.edu 662292SN/A/* 672791Sktlim@umich.edu * This defines the number of longs (32-bits on 32 bit machines, 682791Sktlim@umich.edu * 64-bit on 64-bit AMD machines) to use to hold the set... 692292SN/A * the default is 4, allowing 128 or 256 different members 702683Sktlim@umich.edu * of the set. 712862Sktlim@umich.edu * 722862Sktlim@umich.edu * This should never need to be changed for correctness reasons, 732862Sktlim@umich.edu * though increasing it will increase performance for larger 742862Sktlim@umich.edu * set sizes at the cost of a (much) larger memory footprint 752683Sktlim@umich.edu * 762683Sktlim@umich.edu */ 772683Sktlim@umich.educonst int NUMBER_WORDS_PER_SET = 4; 782683Sktlim@umich.edu 792683Sktlim@umich.edu 802683Sktlim@umich.edustruct RubyObjConf { 812683Sktlim@umich.edu string type; 822683Sktlim@umich.edu string name; 832683Sktlim@umich.edu vector<string> argv; 842683Sktlim@umich.edu RubyObjConf(string _type, string _name, vector<string> _argv) 852683Sktlim@umich.edu : type(_type), name(_name), argv(_argv) 862683Sktlim@umich.edu {} 872683Sktlim@umich.edu}; 882683Sktlim@umich.edu 892683Sktlim@umich.educlass RubySystem : public SimObject { 902683Sktlim@umich.edupublic: 912683Sktlim@umich.edu typedef RubySystemParams Params; 922683Sktlim@umich.edu RubySystem(const Params *p); 932683Sktlim@umich.edu // Destructor 942683Sktlim@umich.edu ~RubySystem(); 952683Sktlim@umich.edu 962683Sktlim@umich.edu // config accessors 972683Sktlim@umich.edu static int getRandomSeed() { return m_random_seed; } 982690Sktlim@umich.edu static int getRandomization() { return m_randomization; } 992690Sktlim@umich.edu static int getTechNm() { return m_tech_nm; } 1002683Sktlim@umich.edu static int getFreqMhz() { return m_freq_mhz; } 1012683Sktlim@umich.edu static int getBlockSizeBytes() { return m_block_size_bytes; } 1022690Sktlim@umich.edu static int getBlockSizeBits() { return m_block_size_bits; } 1032690Sktlim@umich.edu static uint64 getMemorySizeBytes() { return m_memory_size_bytes; } 1042683Sktlim@umich.edu static int getMemorySizeBits() { return m_memory_size_bits; } 1052683Sktlim@umich.edu 1062683Sktlim@umich.edu // Public Methods 1072683Sktlim@umich.edu static RubyPort* getPortOnly(const string & name) { 1082683Sktlim@umich.edu assert(m_ports.count(name) == 1); return m_ports[name]; } 1092683Sktlim@umich.edu static RubyPort* getPort(const string & name, void (*hit_callback)(int64_t)) { 1102683Sktlim@umich.edu if (m_ports.count(name) != 1){ 1112683Sktlim@umich.edu cerr << "Port " << name << " has " << m_ports.count(name) << " instances" << endl; 1122683Sktlim@umich.edu } 1132683Sktlim@umich.edu assert(m_ports.count(name) == 1); 1142678Sktlim@umich.edu m_ports[name]->registerHitCallback(hit_callback); 1152292SN/A return m_ports[name]; 1162683Sktlim@umich.edu } 1172683Sktlim@umich.edu static Network* getNetwork() { assert(m_network_ptr != NULL); return m_network_ptr; } 1182292SN/A static Topology* getTopology(const string & name) { assert(m_topologies.count(name) == 1); return m_topologies[name]; } 1192683Sktlim@umich.edu static CacheMemory* getCache(const string & name) { assert(m_caches.count(name) == 1); return m_caches[name]; } 1202683Sktlim@umich.edu static DirectoryMemory* getDirectory(const string & name) { assert(m_directories.count(name) == 1); return m_directories[name]; } 1212683Sktlim@umich.edu static MemoryControl* getMemoryControl(const string & name) { assert(m_memorycontrols.count(name) == 1); return m_memorycontrols[name]; } 1222683Sktlim@umich.edu static Sequencer* getSequencer(const string & name) { assert(m_sequencers.count(name) == 1); return m_sequencers[name]; } 1232683Sktlim@umich.edu static DMASequencer* getDMASequencer(const string & name) { assert(m_dma_sequencers.count(name) == 1); return m_dma_sequencers[name]; } 1242683Sktlim@umich.edu static AbstractController* getController(const string & name) { assert(m_controllers.count(name) == 1); return m_controllers[name]; } 1252683Sktlim@umich.edu 1262683Sktlim@umich.edu static RubyEventQueue* getEventQueue() { return g_eventQueue_ptr; } 1272683Sktlim@umich.edu 1282683Sktlim@umich.edu static int getNumberOfDirectories() { return m_directories.size(); } 1292683Sktlim@umich.edu static int getNumberOfSequencers() { return m_sequencers.size(); } 1302683Sktlim@umich.edu 1312683Sktlim@umich.edu Profiler* getProfiler() {assert(m_profiler_ptr != NULL); return m_profiler_ptr; } 1322683Sktlim@umich.edu static Tracer* getTracer() { assert(m_tracer_ptr != NULL); return m_tracer_ptr; } 1332683Sktlim@umich.edu static MemoryVector* getMemoryVector() { assert(m_mem_vec_ptr != NULL); return m_mem_vec_ptr;} 1342683Sktlim@umich.edu 1352683Sktlim@umich.edu void recordCacheContents(CacheRecorder& tr) const; 1362683Sktlim@umich.edu static void printConfig(ostream& out); 1372683Sktlim@umich.edu static void printStats(ostream& out); 1382683Sktlim@umich.edu void clearStats() const; 1392683Sktlim@umich.edu 1402683Sktlim@umich.edu uint64 getInstructionCount(int thread) { return 1; } 1412683Sktlim@umich.edu static uint64 getCycleCount(int thread) { return g_eventQueue_ptr->getTime(); } 1422683Sktlim@umich.edu 1432683Sktlim@umich.edu void print(ostream& out) const; 1442683Sktlim@umich.edu /* 1452683Sktlim@umich.edu#ifdef CHECK_COHERENCE 1462683Sktlim@umich.edu void checkGlobalCoherenceInvariant(const Address& addr); 1472683Sktlim@umich.edu#endif 1482683Sktlim@umich.edu */ 1492683Sktlim@umich.edu 1502683Sktlim@umich.eduprivate: 1512683Sktlim@umich.edu // Constructors 1522683Sktlim@umich.edu RubySystem(const vector <RubyObjConf> & cfg_file); 1532683Sktlim@umich.edu 1542683Sktlim@umich.edu // Private copy constructor and assignment operator 1552683Sktlim@umich.edu RubySystem(const RubySystem& obj); 1562683Sktlim@umich.edu RubySystem& operator=(const RubySystem& obj); 1572683Sktlim@umich.edu 1582292SN/A void init(); 1592292SN/A 1602292SN/A static void printSystemConfig(ostream& out); 1612292SN/A 1622292SN/Aprivate: 1632690Sktlim@umich.edu // configuration parameters 1642683Sktlim@umich.edu static int m_random_seed; 1652683Sktlim@umich.edu static bool m_randomization; 1662292SN/A static int m_tech_nm; 1672683Sktlim@umich.edu static int m_freq_mhz; 1682683Sktlim@umich.edu static int m_block_size_bytes; 1692292SN/A static int m_block_size_bits; 1702292SN/A static uint64 m_memory_size_bytes; 1712683Sktlim@umich.edu static int m_memory_size_bits; 1722292SN/A 1732292SN/A // Data Members (m_ prefix) 1742292SN/A static Network* m_network_ptr; 1752292SN/A static map< string, Topology* > m_topologies; 1762292SN/A static map< string, RubyPort* > m_ports; 1772330SN/A static map< string, CacheMemory* > m_caches; 1782683Sktlim@umich.edu static map< string, DirectoryMemory* > m_directories; 1792683Sktlim@umich.edu static map< string, Sequencer* > m_sequencers; 1802683Sktlim@umich.edu static map< string, DMASequencer* > m_dma_sequencers; 1812683Sktlim@umich.edu static map< string, AbstractController* > m_controllers; 1822683Sktlim@umich.edu static map< string, MemoryControl* > m_memorycontrols; 1832683Sktlim@umich.edu 1842683Sktlim@umich.edu //added by SS 1852683Sktlim@umich.edu //static map< string, Tracer* > m_tracers; 1862292SN/A 1872678Sktlim@umich.edupublic: 1882678Sktlim@umich.edu static Profiler* m_profiler_ptr; 1892292SN/A static Tracer* m_tracer_ptr; 1902292SN/A static MemoryVector* m_mem_vec_ptr; 1912292SN/A}; 1922292SN/A 1932292SN/A// Output operator declaration 1942292SN/Aostream& operator<<(ostream& out, const RubySystem& obj); 1952330SN/A 1962330SN/A// ******************* Definitions ******************* 1972330SN/A 1982683Sktlim@umich.edu// Output operator definition 1992683Sktlim@umich.eduinline 2002683Sktlim@umich.eduostream& operator<<(ostream& out, const RubySystem& obj) 2012683Sktlim@umich.edu{ 2022292SN/A// obj.print(out); 2033276Sgblack@eecs.umich.edu out << flush; 2043276Sgblack@eecs.umich.edu return out; 2053276Sgblack@eecs.umich.edu} 2063276Sgblack@eecs.umich.edu 2073276Sgblack@eecs.umich.edu#endif //SYSTEM_H 2083276Sgblack@eecs.umich.edu 2093276Sgblack@eecs.umich.edu 2103276Sgblack@eecs.umich.edu 2113276Sgblack@eecs.umich.edu