RubyPort.hh revision 9508:dde110931867
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 44 45#include <cassert> 46#include <string> 47 48#include "mem/protocol/RequestStatus.hh" 49#include "mem/ruby/buffers/MessageBuffer.hh" 50#include "mem/ruby/system/System.hh" 51#include "mem/mem_object.hh" 52#include "mem/physical.hh" 53#include "mem/tport.hh" 54#include "params/RubyPort.hh" 55 56class AbstractController; 57 58class RubyPort : public MemObject 59{ 60 public: 61 class M5Port : public QueuedSlavePort 62 { 63 private: 64 65 SlavePacketQueue queue; 66 RubyPort *ruby_port; 67 RubySystem* ruby_system; 68 bool _onRetryList; 69 bool access_phys_mem; 70 71 public: 72 M5Port(const std::string &_name, RubyPort *_port, 73 RubySystem*_system, bool _access_phys_mem); 74 void hitCallback(PacketPtr pkt); 75 void evictionCallback(const Address& address); 76 unsigned deviceBlockSize() const; 77 78 bool onRetryList() 79 { return _onRetryList; } 80 81 void onRetryList(bool newVal) 82 { _onRetryList = newVal; } 83 84 protected: 85 virtual bool recvTimingReq(PacketPtr pkt); 86 virtual Tick recvAtomic(PacketPtr pkt); 87 virtual void recvFunctional(PacketPtr pkt); 88 virtual AddrRangeList getAddrRanges() const; 89 90 private: 91 bool isPhysMemAddress(Addr addr); 92 }; 93 94 friend class M5Port; 95 96 class PioPort : public QueuedMasterPort 97 { 98 private: 99 100 MasterPacketQueue queue; 101 102 RubyPort *ruby_port; 103 104 public: 105 PioPort(const std::string &_name, RubyPort *_port); 106 107 protected: 108 virtual bool recvTimingResp(PacketPtr pkt); 109 }; 110 111 friend class PioPort; 112 113 struct SenderState : public Packet::SenderState 114 { 115 M5Port* port; 116 Packet::SenderState *saved; 117 118 SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL) 119 : port(_port), saved(sender_state) 120 {} 121 }; 122 123 typedef RubyPortParams Params; 124 RubyPort(const Params *p); 125 virtual ~RubyPort() {} 126 127 void init(); 128 129 BaseMasterPort &getMasterPort(const std::string &if_name, 130 PortID idx = InvalidPortID); 131 BaseSlavePort &getSlavePort(const std::string &if_name, 132 PortID idx = InvalidPortID); 133 134 virtual RequestStatus makeRequest(PacketPtr pkt) = 0; 135 virtual int outstandingCount() const = 0; 136 virtual bool isDeadlockEventScheduled() const = 0; 137 virtual void descheduleDeadlockEvent() = 0; 138 139 // 140 // Called by the controller to give the sequencer a pointer. 141 // A pointer to the controller is needed for atomic support. 142 // 143 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 144 int getId() { return m_version; } 145 unsigned int drain(DrainManager *dm); 146 147 protected: 148 const std::string m_name; 149 void ruby_hit_callback(PacketPtr pkt); 150 void testDrainComplete(); 151 void ruby_eviction_callback(const Address& address); 152 153 int m_version; 154 AbstractController* m_controller; 155 MessageBuffer* m_mandatory_q_ptr; 156 PioPort pio_port; 157 bool m_usingRubyTester; 158 159 private: 160 void addToRetryList(M5Port * port) 161 { 162 if (!port->onRetryList()) { 163 port->onRetryList(true); 164 retryList.push_back(port); 165 waitingOnSequencer = true; 166 } 167 } 168 169 unsigned int getChildDrainCount(DrainManager *dm); 170 171 uint16_t m_port_id; 172 uint64_t m_request_cnt; 173 174 /** Vector of M5 Ports attached to this Ruby port. */ 175 typedef std::vector<M5Port*>::iterator CpuPortIter; 176 std::vector<M5Port*> slave_ports; 177 std::vector<PioPort*> master_ports; 178 179 DrainManager *drainManager; 180 181 RubySystem* ruby_system; 182 System* system; 183 184 // 185 // Based on similar code in the M5 bus. Stores pointers to those ports 186 // that should be called when the Sequencer becomes available after a stall. 187 // 188 std::list<M5Port*> retryList; 189 190 bool waitingOnSequencer; 191 bool access_phys_mem; 192}; 193 194#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 195