RubyPort.hh revision 9090 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/system/System.hh"
50#include "mem/mem_object.hh"
51#include "mem/physical.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class MessageBuffer;
56class AbstractController;
57
58class RubyPort : public MemObject
59{
60  public:
61    class M5Port : public QueuedSlavePort
62    {
63      private:
64
65        SlavePacketQueue queue;
66        RubyPort *ruby_port;
67        RubySystem* ruby_system;
68        bool _onRetryList;
69        bool access_phys_mem;
70
71      public:
72        M5Port(const std::string &_name, RubyPort *_port,
73               RubySystem*_system, bool _access_phys_mem);
74        bool sendNextCycle(PacketPtr pkt, bool send_as_snoop = false);
75        void hitCallback(PacketPtr pkt);
76        void evictionCallback(const Address& address);
77        unsigned deviceBlockSize() const;
78
79        bool onRetryList()
80        { return _onRetryList; }
81
82        void onRetryList(bool newVal)
83        { _onRetryList = newVal; }
84
85      protected:
86        virtual bool recvTimingReq(PacketPtr pkt);
87        virtual Tick recvAtomic(PacketPtr pkt);
88        virtual void recvFunctional(PacketPtr pkt);
89        virtual AddrRangeList getAddrRanges() const;
90
91      private:
92        bool isPhysMemAddress(Addr addr);
93        bool doFunctionalRead(PacketPtr pkt);
94        bool doFunctionalWrite(PacketPtr pkt);
95    };
96
97    friend class M5Port;
98
99    class PioPort : public QueuedMasterPort
100    {
101      private:
102
103        MasterPacketQueue queue;
104
105        RubyPort *ruby_port;
106
107      public:
108        PioPort(const std::string &_name, RubyPort *_port);
109        bool sendNextCycle(PacketPtr pkt);
110
111      protected:
112        virtual bool recvTimingResp(PacketPtr pkt);
113    };
114
115    friend class PioPort;
116
117    struct SenderState : public Packet::SenderState
118    {
119        M5Port* port;
120        Packet::SenderState *saved;
121
122        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
123            : port(_port), saved(sender_state)
124        {}
125    };
126
127    typedef RubyPortParams Params;
128    RubyPort(const Params *p);
129    virtual ~RubyPort() {}
130
131    void init();
132
133    MasterPort &getMasterPort(const std::string &if_name, int idx);
134    SlavePort &getSlavePort(const std::string &if_name, int idx);
135
136    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
137    virtual int outstandingCount() const = 0;
138    virtual bool isDeadlockEventScheduled() const = 0;
139    virtual void descheduleDeadlockEvent() = 0;
140
141    //
142    // Called by the controller to give the sequencer a pointer.
143    // A pointer to the controller is needed for atomic support.
144    //
145    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
146    int getId() { return m_version; }
147    unsigned int drain(Event *de);
148
149  protected:
150    const std::string m_name;
151    void ruby_hit_callback(PacketPtr pkt);
152    void testDrainComplete();
153    void ruby_eviction_callback(const Address& address);
154
155    int m_version;
156    AbstractController* m_controller;
157    MessageBuffer* m_mandatory_q_ptr;
158    PioPort pio_port;
159    bool m_usingRubyTester;
160
161  private:
162    void addToRetryList(M5Port * port)
163    {
164        if (!port->onRetryList()) {
165            port->onRetryList(true);
166            retryList.push_back(port);
167            waitingOnSequencer = true;
168        }
169    }
170
171    unsigned int getDrainCount(Event *de);
172
173    uint16_t m_port_id;
174    uint64_t m_request_cnt;
175
176    /** Vector of M5 Ports attached to this Ruby port. */
177    typedef std::vector<M5Port*>::iterator CpuPortIter;
178    std::vector<M5Port*> slave_ports;
179    std::vector<PioPort*> master_ports;
180
181    Event *drainEvent;
182
183    RubySystem* ruby_system;
184    System* system;
185
186    //
187    // Based on similar code in the M5 bus.  Stores pointers to those ports
188    // that should be called when the Sequencer becomes available after a stall.
189    //
190    std::list<M5Port*> retryList;
191
192    bool waitingOnSequencer;
193    bool access_phys_mem;
194};
195
196#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
197