RubyPort.hh revision 8688 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/protocol/RequestStatus.hh"
36#include "mem/ruby/system/System.hh"
37#include "mem/mem_object.hh"
38#include "mem/physical.hh"
39#include "mem/tport.hh"
40#include "params/RubyPort.hh"
41
42class MessageBuffer;
43class AbstractController;
44
45class RubyPort : public MemObject
46{
47  public:
48    class M5Port : public SimpleTimingPort
49    {
50      private:
51        RubyPort *ruby_port;
52        RubySystem* ruby_system;
53        bool _onRetryList;
54        bool access_phys_mem;
55
56      public:
57        M5Port(const std::string &_name, RubyPort *_port,
58               RubySystem*_system, bool _access_phys_mem);
59        bool sendTiming(PacketPtr pkt);
60        void hitCallback(PacketPtr pkt);
61        unsigned deviceBlockSize() const;
62
63        bool onRetryList()
64        { return _onRetryList; }
65
66        void onRetryList(bool newVal)
67        { _onRetryList = newVal; }
68
69      protected:
70        virtual bool recvTiming(PacketPtr pkt);
71        virtual Tick recvAtomic(PacketPtr pkt);
72        virtual void recvFunctional(PacketPtr pkt);
73
74      private:
75        bool isPhysMemAddress(Addr addr);
76        bool doFunctionalRead(PacketPtr pkt);
77        bool doFunctionalWrite(PacketPtr pkt);
78    };
79
80    friend class M5Port;
81
82    class PioPort : public SimpleTimingPort
83    {
84      private:
85        RubyPort *ruby_port;
86
87      public:
88        PioPort(const std::string &_name, RubyPort *_port);
89        bool sendTiming(PacketPtr pkt);
90
91      protected:
92        virtual bool recvTiming(PacketPtr pkt);
93        virtual Tick recvAtomic(PacketPtr pkt);
94    };
95
96    friend class PioPort;
97
98    struct SenderState : public Packet::SenderState
99    {
100        M5Port* port;
101        Packet::SenderState *saved;
102
103        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
104            : port(_port), saved(sender_state)
105        {}
106    };
107
108    typedef RubyPortParams Params;
109    RubyPort(const Params *p);
110    virtual ~RubyPort() {}
111
112    void init();
113
114    Port *getPort(const std::string &if_name, int idx);
115
116    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
117    virtual int outstandingCount() const = 0;
118    virtual bool isDeadlockEventScheduled() const = 0;
119    virtual void descheduleDeadlockEvent() = 0;
120
121    //
122    // Called by the controller to give the sequencer a pointer.
123    // A pointer to the controller is needed for atomic support.
124    //
125    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
126    int getId() { return m_version; }
127    unsigned int drain(Event *de);
128
129  protected:
130    const std::string m_name;
131    void ruby_hit_callback(PacketPtr pkt);
132    void hit(PacketPtr pkt);
133    void testDrainComplete();
134
135    int m_version;
136    AbstractController* m_controller;
137    MessageBuffer* m_mandatory_q_ptr;
138    PioPort* pio_port;
139    bool m_usingRubyTester;
140
141  private:
142    void addToRetryList(M5Port * port)
143    {
144        if (!port->onRetryList()) {
145            port->onRetryList(true);
146            retryList.push_back(port);
147            waitingOnSequencer = true;
148        }
149    }
150
151    unsigned int getDrainCount(Event *de);
152
153    uint16_t m_port_id;
154    uint64_t m_request_cnt;
155
156    M5Port* physMemPort;
157
158    /*! Vector of CPU Port attached to this Ruby port. */
159    typedef std::vector<M5Port*>::iterator CpuPortIter;
160    std::vector<M5Port*> cpu_ports;
161
162    Event *drainEvent;
163
164    PhysicalMemory* physmem;
165    RubySystem* ruby_system;
166
167    //
168    // Based on similar code in the M5 bus.  Stores pointers to those ports
169    // that should be called when the Sequencer becomes available after a stall.
170    //
171    std::list<M5Port*> retryList;
172
173    bool waitingOnSequencer;
174    bool access_phys_mem;
175};
176
177#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
178