RubyPort.hh revision 10875 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/network/MessageBuffer.hh"
50#include "mem/ruby/system/System.hh"
51#include "mem/mem_object.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class AbstractController;
56
57class RubyPort : public MemObject
58{
59  public:
60    class MemMasterPort : public QueuedMasterPort
61    {
62      private:
63        ReqPacketQueue reqQueue;
64        SnoopRespPacketQueue snoopRespQueue;
65
66      public:
67        MemMasterPort(const std::string &_name, RubyPort *_port);
68
69      protected:
70        bool recvTimingResp(PacketPtr pkt);
71        void recvRangeChange() {}
72    };
73
74    class MemSlavePort : public QueuedSlavePort
75    {
76      private:
77        RespPacketQueue queue;
78        RubySystem* ruby_system;
79        bool access_backing_store;
80
81      public:
82        MemSlavePort(const std::string &_name, RubyPort *_port,
83               RubySystem*_system, bool _access_backing_store, PortID id);
84        void hitCallback(PacketPtr pkt);
85        void evictionCallback(const Address& address);
86
87      protected:
88        bool recvTimingReq(PacketPtr pkt);
89
90        Tick recvAtomic(PacketPtr pkt)
91        { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }
92
93        void recvFunctional(PacketPtr pkt);
94
95        AddrRangeList getAddrRanges() const
96        { AddrRangeList ranges; return ranges; }
97
98      private:
99        bool isPhysMemAddress(Addr addr) const;
100    };
101
102    class PioMasterPort : public QueuedMasterPort
103    {
104      private:
105        ReqPacketQueue reqQueue;
106        SnoopRespPacketQueue snoopRespQueue;
107
108      public:
109        PioMasterPort(const std::string &_name, RubyPort *_port);
110
111      protected:
112        bool recvTimingResp(PacketPtr pkt);
113        void recvRangeChange();
114    };
115
116    class PioSlavePort : public QueuedSlavePort
117    {
118      private:
119        RespPacketQueue queue;
120
121      public:
122        PioSlavePort(const std::string &_name, RubyPort *_port);
123
124      protected:
125        bool recvTimingReq(PacketPtr pkt);
126
127        Tick recvAtomic(PacketPtr pkt)
128        { panic("recvAtomic not supported with ruby!"); }
129
130        void recvFunctional(PacketPtr pkt)
131        { panic("recvFunctional should never be called on pio slave port!"); }
132
133        AddrRangeList getAddrRanges() const;
134    };
135
136    struct SenderState : public Packet::SenderState
137    {
138        MemSlavePort *port;
139        SenderState(MemSlavePort * _port) : port(_port)
140        {}
141     };
142
143    typedef RubyPortParams Params;
144    RubyPort(const Params *p);
145    virtual ~RubyPort() {}
146
147    void init();
148
149    BaseMasterPort &getMasterPort(const std::string &if_name,
150                                  PortID idx = InvalidPortID);
151    BaseSlavePort &getSlavePort(const std::string &if_name,
152                                PortID idx = InvalidPortID);
153
154    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
155    virtual int outstandingCount() const = 0;
156    virtual bool isDeadlockEventScheduled() const = 0;
157    virtual void descheduleDeadlockEvent() = 0;
158
159    //
160    // Called by the controller to give the sequencer a pointer.
161    // A pointer to the controller is needed for atomic support.
162    //
163    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
164    uint32_t getId() { return m_version; }
165    unsigned int drain(DrainManager *dm);
166
167  protected:
168    void ruby_hit_callback(PacketPtr pkt);
169    void testDrainComplete();
170    void ruby_eviction_callback(const Address& address);
171
172    /**
173     * Called by the PIO port when receiving a timing response.
174     *
175     * @param pkt Response packet
176     * @param master_port_id Port id of the PIO port
177     *
178     * @return Whether successfully sent
179     */
180    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
181
182    uint32_t m_version;
183    AbstractController* m_controller;
184    MessageBuffer* m_mandatory_q_ptr;
185    bool m_usingRubyTester;
186    System* system;
187
188  private:
189    void addToRetryList(MemSlavePort * port)
190    {
191        if (std::find(retryList.begin(), retryList.end(), port) !=
192               retryList.end()) return;
193        retryList.push_back(port);
194    }
195
196    unsigned int getChildDrainCount(DrainManager *dm);
197
198    PioMasterPort pioMasterPort;
199    PioSlavePort pioSlavePort;
200    MemMasterPort memMasterPort;
201    MemSlavePort memSlavePort;
202    unsigned int gotAddrRanges;
203
204    /** Vector of M5 Ports attached to this Ruby port. */
205    typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
206    std::vector<MemSlavePort *> slave_ports;
207    std::vector<PioMasterPort *> master_ports;
208
209    DrainManager *drainManager;
210
211    //
212    // Based on similar code in the M5 bus.  Stores pointers to those ports
213    // that should be called when the Sequencer becomes available after a stall.
214    //
215    std::vector<MemSlavePort *> retryList;
216};
217
218#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
219