RubyPort.hh revision 9245
16876Ssteve.reinhardt@amd.com/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427039Snate@binkert.org#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 437039Snate@binkert.org#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 446285Snate@binkert.org 457039Snate@binkert.org#include <cassert> 466285Snate@binkert.org#include <string> 476285Snate@binkert.org 486922SBrad.Beckmann@amd.com#include "mem/protocol/RequestStatus.hh" 497909Shestness@cs.utexas.edu#include "mem/ruby/system/System.hh" 508229Snate@binkert.org#include "mem/mem_object.hh" 518229Snate@binkert.org#include "mem/physical.hh" 527039Snate@binkert.org#include "mem/tport.hh" 536876Ssteve.reinhardt@amd.com#include "params/RubyPort.hh" 546876Ssteve.reinhardt@amd.com 556876Ssteve.reinhardt@amd.comclass MessageBuffer; 566876Ssteve.reinhardt@amd.comclass AbstractController; 576876Ssteve.reinhardt@amd.com 587039Snate@binkert.orgclass RubyPort : public MemObject 597039Snate@binkert.org{ 607039Snate@binkert.org public: 618922Swilliam.wang@arm.com class M5Port : public QueuedSlavePort 626882SBrad.Beckmann@amd.com { 637039Snate@binkert.org private: 648914Sandreas.hansson@arm.com 658975Sandreas.hansson@arm.com SlavePacketQueue queue; 666882SBrad.Beckmann@amd.com RubyPort *ruby_port; 678436SBrad.Beckmann@amd.com RubySystem* ruby_system; 687910SBrad.Beckmann@amd.com bool _onRetryList; 697915SBrad.Beckmann@amd.com bool access_phys_mem; 706882SBrad.Beckmann@amd.com 716882SBrad.Beckmann@amd.com public: 727915SBrad.Beckmann@amd.com M5Port(const std::string &_name, RubyPort *_port, 738436SBrad.Beckmann@amd.com RubySystem*_system, bool _access_phys_mem); 746882SBrad.Beckmann@amd.com void hitCallback(PacketPtr pkt); 758717Snilay@cs.wisc.edu void evictionCallback(const Address& address); 767909Shestness@cs.utexas.edu unsigned deviceBlockSize() const; 777910SBrad.Beckmann@amd.com 787910SBrad.Beckmann@amd.com bool onRetryList() 797910SBrad.Beckmann@amd.com { return _onRetryList; } 807910SBrad.Beckmann@amd.com 817910SBrad.Beckmann@amd.com void onRetryList(bool newVal) 827910SBrad.Beckmann@amd.com { _onRetryList = newVal; } 836882SBrad.Beckmann@amd.com 846882SBrad.Beckmann@amd.com protected: 858975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 866882SBrad.Beckmann@amd.com virtual Tick recvAtomic(PacketPtr pkt); 878436SBrad.Beckmann@amd.com virtual void recvFunctional(PacketPtr pkt); 889090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 896882SBrad.Beckmann@amd.com 906882SBrad.Beckmann@amd.com private: 916882SBrad.Beckmann@amd.com bool isPhysMemAddress(Addr addr); 928436SBrad.Beckmann@amd.com bool doFunctionalRead(PacketPtr pkt); 938436SBrad.Beckmann@amd.com bool doFunctionalWrite(PacketPtr pkt); 946882SBrad.Beckmann@amd.com }; 956882SBrad.Beckmann@amd.com 966882SBrad.Beckmann@amd.com friend class M5Port; 976882SBrad.Beckmann@amd.com 988922Swilliam.wang@arm.com class PioPort : public QueuedMasterPort 996882SBrad.Beckmann@amd.com { 1007039Snate@binkert.org private: 1018914Sandreas.hansson@arm.com 1028975Sandreas.hansson@arm.com MasterPacketQueue queue; 1038914Sandreas.hansson@arm.com 1046882SBrad.Beckmann@amd.com RubyPort *ruby_port; 1056882SBrad.Beckmann@amd.com 1066882SBrad.Beckmann@amd.com public: 1077039Snate@binkert.org PioPort(const std::string &_name, RubyPort *_port); 1086882SBrad.Beckmann@amd.com 1096882SBrad.Beckmann@amd.com protected: 1108975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1116882SBrad.Beckmann@amd.com }; 1126882SBrad.Beckmann@amd.com 1136882SBrad.Beckmann@amd.com friend class PioPort; 1146882SBrad.Beckmann@amd.com 1156882SBrad.Beckmann@amd.com struct SenderState : public Packet::SenderState 1166882SBrad.Beckmann@amd.com { 1176882SBrad.Beckmann@amd.com M5Port* port; 1186882SBrad.Beckmann@amd.com Packet::SenderState *saved; 1196882SBrad.Beckmann@amd.com 1207039Snate@binkert.org SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL) 1216882SBrad.Beckmann@amd.com : port(_port), saved(sender_state) 1226882SBrad.Beckmann@amd.com {} 1236882SBrad.Beckmann@amd.com }; 1246882SBrad.Beckmann@amd.com 1256876Ssteve.reinhardt@amd.com typedef RubyPortParams Params; 1266876Ssteve.reinhardt@amd.com RubyPort(const Params *p); 1276882SBrad.Beckmann@amd.com virtual ~RubyPort() {} 1286882SBrad.Beckmann@amd.com 1296882SBrad.Beckmann@amd.com void init(); 1306285Snate@binkert.org 1318922Swilliam.wang@arm.com MasterPort &getMasterPort(const std::string &if_name, int idx); 1328922Swilliam.wang@arm.com SlavePort &getSlavePort(const std::string &if_name, int idx); 1336876Ssteve.reinhardt@amd.com 1348615Snilay@cs.wisc.edu virtual RequestStatus makeRequest(PacketPtr pkt) = 0; 1358688Snilay@cs.wisc.edu virtual int outstandingCount() const = 0; 1368688Snilay@cs.wisc.edu virtual bool isDeadlockEventScheduled() const = 0; 1378688Snilay@cs.wisc.edu virtual void descheduleDeadlockEvent() = 0; 1386882SBrad.Beckmann@amd.com 1396882SBrad.Beckmann@amd.com // 1406882SBrad.Beckmann@amd.com // Called by the controller to give the sequencer a pointer. 1416882SBrad.Beckmann@amd.com // A pointer to the controller is needed for atomic support. 1426882SBrad.Beckmann@amd.com // 1436882SBrad.Beckmann@amd.com void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 1448688Snilay@cs.wisc.edu int getId() { return m_version; } 1458688Snilay@cs.wisc.edu unsigned int drain(Event *de); 1466285Snate@binkert.org 1477039Snate@binkert.org protected: 1487055Snate@binkert.org const std::string m_name; 1497039Snate@binkert.org void ruby_hit_callback(PacketPtr pkt); 1508688Snilay@cs.wisc.edu void testDrainComplete(); 1518717Snilay@cs.wisc.edu void ruby_eviction_callback(const Address& address); 1526285Snate@binkert.org 1537039Snate@binkert.org int m_version; 1547039Snate@binkert.org AbstractController* m_controller; 1557039Snate@binkert.org MessageBuffer* m_mandatory_q_ptr; 1568851Sandreas.hansson@arm.com PioPort pio_port; 1577910SBrad.Beckmann@amd.com bool m_usingRubyTester; 1586876Ssteve.reinhardt@amd.com 1597039Snate@binkert.org private: 1607910SBrad.Beckmann@amd.com void addToRetryList(M5Port * port) 1617910SBrad.Beckmann@amd.com { 1627910SBrad.Beckmann@amd.com if (!port->onRetryList()) { 1637910SBrad.Beckmann@amd.com port->onRetryList(true); 1647910SBrad.Beckmann@amd.com retryList.push_back(port); 1657910SBrad.Beckmann@amd.com waitingOnSequencer = true; 1667910SBrad.Beckmann@amd.com } 1677910SBrad.Beckmann@amd.com } 1687910SBrad.Beckmann@amd.com 1699245Shestness@cs.wisc.edu unsigned int getChildDrainCount(Event *de); 1708688Snilay@cs.wisc.edu 1716922SBrad.Beckmann@amd.com uint16_t m_port_id; 1726922SBrad.Beckmann@amd.com uint64_t m_request_cnt; 1736882SBrad.Beckmann@amd.com 1748922Swilliam.wang@arm.com /** Vector of M5 Ports attached to this Ruby port. */ 1758686Snilay@cs.wisc.edu typedef std::vector<M5Port*>::iterator CpuPortIter; 1768922Swilliam.wang@arm.com std::vector<M5Port*> slave_ports; 1778922Swilliam.wang@arm.com std::vector<PioPort*> master_ports; 1788686Snilay@cs.wisc.edu 1798688Snilay@cs.wisc.edu Event *drainEvent; 1808688Snilay@cs.wisc.edu 1818436SBrad.Beckmann@amd.com RubySystem* ruby_system; 1828923Sandreas.hansson@arm.com System* system; 1837910SBrad.Beckmann@amd.com 1847910SBrad.Beckmann@amd.com // 1857910SBrad.Beckmann@amd.com // Based on similar code in the M5 bus. Stores pointers to those ports 1867910SBrad.Beckmann@amd.com // that should be called when the Sequencer becomes available after a stall. 1877910SBrad.Beckmann@amd.com // 1887910SBrad.Beckmann@amd.com std::list<M5Port*> retryList; 1897910SBrad.Beckmann@amd.com 1907910SBrad.Beckmann@amd.com bool waitingOnSequencer; 1917915SBrad.Beckmann@amd.com bool access_phys_mem; 1926285Snate@binkert.org}; 1936285Snate@binkert.org 1947039Snate@binkert.org#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 195