RubyPort.hh revision 7909 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/mem_object.hh"
36#include "mem/physical.hh"
37#include "mem/protocol/RequestStatus.hh"
38#include "mem/ruby/libruby.hh"
39#include "mem/ruby/system/System.hh"
40#include "mem/tport.hh"
41#include "params/RubyPort.hh"
42
43class MessageBuffer;
44class AbstractController;
45
46class RubyPort : public MemObject
47{
48  public:
49    class M5Port : public SimpleTimingPort
50    {
51      private:
52        RubyPort *ruby_port;
53
54      public:
55        M5Port(const std::string &_name, RubyPort *_port);
56        bool sendTiming(PacketPtr pkt);
57        void hitCallback(PacketPtr pkt);
58        unsigned deviceBlockSize() const;
59
60      protected:
61        virtual bool recvTiming(PacketPtr pkt);
62        virtual Tick recvAtomic(PacketPtr pkt);
63
64      private:
65        bool isPhysMemAddress(Addr addr);
66    };
67
68    friend class M5Port;
69
70    class PioPort : public SimpleTimingPort
71    {
72      private:
73        RubyPort *ruby_port;
74
75      public:
76        PioPort(const std::string &_name, RubyPort *_port);
77        bool sendTiming(PacketPtr pkt);
78
79      protected:
80        virtual bool recvTiming(PacketPtr pkt);
81        virtual Tick recvAtomic(PacketPtr pkt);
82    };
83
84    friend class PioPort;
85
86    struct SenderState : public Packet::SenderState
87    {
88        M5Port* port;
89        Packet::SenderState *saved;
90
91        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
92            : port(_port), saved(sender_state)
93        {}
94    };
95
96    typedef RubyPortParams Params;
97    RubyPort(const Params *p);
98    virtual ~RubyPort() {}
99
100    void init();
101
102    Port *getPort(const std::string &if_name, int idx);
103
104    virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
105
106    //
107    // Called by the controller to give the sequencer a pointer.
108    // A pointer to the controller is needed for atomic support.
109    //
110    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
111
112  protected:
113    const std::string m_name;
114    void ruby_hit_callback(PacketPtr pkt);
115    void hit(PacketPtr pkt);
116
117    int m_version;
118    AbstractController* m_controller;
119    MessageBuffer* m_mandatory_q_ptr;
120    PioPort* pio_port;
121
122  private:
123    uint16_t m_port_id;
124    uint64_t m_request_cnt;
125
126    M5Port* physMemPort;
127
128    PhysicalMemory* physmem;
129};
130
131#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
132