RubyPort.hh revision 12395
19913Ssteve.reinhardt@amd.com/* 29913Ssteve.reinhardt@amd.com * Copyright (c) 2012-2013 ARM Limited 39913Ssteve.reinhardt@amd.com * All rights reserved. 49913Ssteve.reinhardt@amd.com * 59913Ssteve.reinhardt@amd.com * The license below extends only to copyright in the software and shall 69913Ssteve.reinhardt@amd.com * not be construed as granting a license to any other intellectual 79913Ssteve.reinhardt@amd.com * property including but not limited to intellectual property relating 89913Ssteve.reinhardt@amd.com * to a hardware implementation of the functionality of the software 99913Ssteve.reinhardt@amd.com * licensed hereunder. You may use the software subject to the license 109913Ssteve.reinhardt@amd.com * terms below provided that you ensure that this notice is replicated 119913Ssteve.reinhardt@amd.com * unmodified and in its entirety in all distributions of the software, 129913Ssteve.reinhardt@amd.com * modified or unmodified, in source code or in binary form. 139913Ssteve.reinhardt@amd.com * 149913Ssteve.reinhardt@amd.com * Copyright (c) 2009-2013 Advanced Micro Devices, Inc. 159913Ssteve.reinhardt@amd.com * Copyright (c) 2011 Mark D. Hill and David A. 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IN NO EVENT SHALL THE COPYRIGHT 339913Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349913Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359913Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369913Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379913Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389913Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399913Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409913Ssteve.reinhardt@amd.com */ 419913Ssteve.reinhardt@amd.com 429913Ssteve.reinhardt@amd.com#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 439913Ssteve.reinhardt@amd.com#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 449920Syasuko.eckert@amd.com 459913Ssteve.reinhardt@amd.com#include <cassert> 469913Ssteve.reinhardt@amd.com#include <string> 479913Ssteve.reinhardt@amd.com 489913Ssteve.reinhardt@amd.com#include "mem/protocol/RequestStatus.hh" 499913Ssteve.reinhardt@amd.com#include "mem/ruby/common/MachineID.hh" 509913Ssteve.reinhardt@amd.com#include "mem/ruby/network/MessageBuffer.hh" 519913Ssteve.reinhardt@amd.com#include "mem/ruby/system/RubySystem.hh" 529913Ssteve.reinhardt@amd.com#include "mem/mem_object.hh" 539913Ssteve.reinhardt@amd.com#include "mem/tport.hh" 549913Ssteve.reinhardt@amd.com#include "params/RubyPort.hh" 559913Ssteve.reinhardt@amd.com 569913Ssteve.reinhardt@amd.comclass AbstractController; 579913Ssteve.reinhardt@amd.com 589913Ssteve.reinhardt@amd.comclass RubyPort : public MemObject 599913Ssteve.reinhardt@amd.com{ 609913Ssteve.reinhardt@amd.com public: 619913Ssteve.reinhardt@amd.com class MemMasterPort : public QueuedMasterPort 629913Ssteve.reinhardt@amd.com { 639913Ssteve.reinhardt@amd.com private: 649913Ssteve.reinhardt@amd.com ReqPacketQueue reqQueue; 659913Ssteve.reinhardt@amd.com SnoopRespPacketQueue snoopRespQueue; 669913Ssteve.reinhardt@amd.com 679913Ssteve.reinhardt@amd.com public: 689913Ssteve.reinhardt@amd.com MemMasterPort(const std::string &_name, RubyPort *_port); 699918Ssteve.reinhardt@amd.com 709913Ssteve.reinhardt@amd.com protected: 719913Ssteve.reinhardt@amd.com bool recvTimingResp(PacketPtr pkt); 729913Ssteve.reinhardt@amd.com void recvRangeChange() {} 739918Ssteve.reinhardt@amd.com }; 749913Ssteve.reinhardt@amd.com 759913Ssteve.reinhardt@amd.com class MemSlavePort : public QueuedSlavePort 769920Syasuko.eckert@amd.com { 779913Ssteve.reinhardt@amd.com private: 789918Ssteve.reinhardt@amd.com RespPacketQueue queue; 799920Syasuko.eckert@amd.com bool access_backing_store; 809920Syasuko.eckert@amd.com bool no_retry_on_stall; 819920Syasuko.eckert@amd.com 829920Syasuko.eckert@amd.com public: 839920Syasuko.eckert@amd.com MemSlavePort(const std::string &_name, RubyPort *_port, 849920Syasuko.eckert@amd.com bool _access_backing_store, 859913Ssteve.reinhardt@amd.com PortID id, bool _no_retry_on_stall); 869913Ssteve.reinhardt@amd.com void hitCallback(PacketPtr pkt); 879918Ssteve.reinhardt@amd.com void evictionCallback(Addr address); 889913Ssteve.reinhardt@amd.com 899913Ssteve.reinhardt@amd.com protected: 909913Ssteve.reinhardt@amd.com bool recvTimingReq(PacketPtr pkt); 919913Ssteve.reinhardt@amd.com 929913Ssteve.reinhardt@amd.com Tick recvAtomic(PacketPtr pkt); 939913Ssteve.reinhardt@amd.com 949913Ssteve.reinhardt@amd.com void recvFunctional(PacketPtr pkt); 959913Ssteve.reinhardt@amd.com 969913Ssteve.reinhardt@amd.com AddrRangeList getAddrRanges() const 979913Ssteve.reinhardt@amd.com { AddrRangeList ranges; return ranges; } 989913Ssteve.reinhardt@amd.com 999913Ssteve.reinhardt@amd.com void addToRetryList(); 100 101 private: 102 bool isPhysMemAddress(Addr addr) const; 103 }; 104 105 class PioMasterPort : public QueuedMasterPort 106 { 107 private: 108 ReqPacketQueue reqQueue; 109 SnoopRespPacketQueue snoopRespQueue; 110 111 public: 112 PioMasterPort(const std::string &_name, RubyPort *_port); 113 114 protected: 115 bool recvTimingResp(PacketPtr pkt); 116 void recvRangeChange(); 117 }; 118 119 class PioSlavePort : public QueuedSlavePort 120 { 121 private: 122 RespPacketQueue queue; 123 124 public: 125 PioSlavePort(const std::string &_name, RubyPort *_port); 126 127 protected: 128 bool recvTimingReq(PacketPtr pkt); 129 130 Tick recvAtomic(PacketPtr pkt); 131 132 void recvFunctional(PacketPtr pkt) 133 { panic("recvFunctional should never be called on pio slave port!"); } 134 135 AddrRangeList getAddrRanges() const; 136 }; 137 138 struct SenderState : public Packet::SenderState 139 { 140 MemSlavePort *port; 141 SenderState(MemSlavePort * _port) : port(_port) 142 {} 143 }; 144 145 typedef RubyPortParams Params; 146 RubyPort(const Params *p); 147 virtual ~RubyPort() {} 148 149 void init() override; 150 151 BaseMasterPort &getMasterPort(const std::string &if_name, 152 PortID idx = InvalidPortID) override; 153 BaseSlavePort &getSlavePort(const std::string &if_name, 154 PortID idx = InvalidPortID) override; 155 156 virtual RequestStatus makeRequest(PacketPtr pkt) = 0; 157 virtual int outstandingCount() const = 0; 158 virtual bool isDeadlockEventScheduled() const = 0; 159 virtual void descheduleDeadlockEvent() = 0; 160 161 // 162 // Called by the controller to give the sequencer a pointer. 163 // A pointer to the controller is needed for atomic support. 164 // 165 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 166 uint32_t getId() { return m_version; } 167 DrainState drain() override; 168 169 bool isCPUSequencer() { return m_isCPUSequencer; } 170 171 protected: 172 void trySendRetries(); 173 void ruby_hit_callback(PacketPtr pkt); 174 void testDrainComplete(); 175 void ruby_eviction_callback(Addr address); 176 177 /** 178 * Called by the PIO port when receiving a timing response. 179 * 180 * @param pkt Response packet 181 * @param master_port_id Port id of the PIO port 182 * 183 * @return Whether successfully sent 184 */ 185 bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 186 187 RubySystem *m_ruby_system; 188 uint32_t m_version; 189 AbstractController* m_controller; 190 MessageBuffer* m_mandatory_q_ptr; 191 bool m_usingRubyTester; 192 System* system; 193 194 std::vector<MemSlavePort *> slave_ports; 195 196 private: 197 bool onRetryList(MemSlavePort * port) 198 { 199 return (std::find(retryList.begin(), retryList.end(), port) != 200 retryList.end()); 201 } 202 void addToRetryList(MemSlavePort * port) 203 { 204 if (onRetryList(port)) return; 205 retryList.push_back(port); 206 } 207 208 PioMasterPort pioMasterPort; 209 PioSlavePort pioSlavePort; 210 MemMasterPort memMasterPort; 211 MemSlavePort memSlavePort; 212 unsigned int gotAddrRanges; 213 214 /** Vector of M5 Ports attached to this Ruby port. */ 215 typedef std::vector<MemSlavePort *>::iterator CpuPortIter; 216 std::vector<PioMasterPort *> master_ports; 217 218 // 219 // Based on similar code in the M5 bus. Stores pointers to those ports 220 // that should be called when the Sequencer becomes available after a stall. 221 // 222 std::vector<MemSlavePort *> retryList; 223 224 bool m_isCPUSequencer; 225}; 226 227#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 228