RubyPort.hh revision 10525 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/network/MessageBuffer.hh"
50#include "mem/ruby/system/System.hh"
51#include "mem/mem_object.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class AbstractController;
56
57class RubyPort : public MemObject
58{
59  public:
60    class MemMasterPort : public QueuedMasterPort
61    {
62      private:
63        MasterPacketQueue queue;
64
65      public:
66        MemMasterPort(const std::string &_name, RubyPort *_port);
67
68      protected:
69        bool recvTimingResp(PacketPtr pkt);
70        void recvRangeChange() {}
71    };
72
73    class MemSlavePort : public QueuedSlavePort
74    {
75      private:
76        SlavePacketQueue queue;
77        RubySystem* ruby_system;
78        bool access_backing_store;
79
80      public:
81        MemSlavePort(const std::string &_name, RubyPort *_port,
82               RubySystem*_system, bool _access_backing_store, PortID id);
83        void hitCallback(PacketPtr pkt);
84        void evictionCallback(const Address& address);
85
86      protected:
87        bool recvTimingReq(PacketPtr pkt);
88
89        Tick recvAtomic(PacketPtr pkt)
90        { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }
91
92        void recvFunctional(PacketPtr pkt);
93
94        AddrRangeList getAddrRanges() const
95        { AddrRangeList ranges; return ranges; }
96
97      private:
98        bool isPhysMemAddress(Addr addr) const;
99    };
100
101    class PioMasterPort : public QueuedMasterPort
102    {
103      private:
104        MasterPacketQueue queue;
105
106      public:
107        PioMasterPort(const std::string &_name, RubyPort *_port);
108
109      protected:
110        bool recvTimingResp(PacketPtr pkt);
111        void recvRangeChange();
112    };
113
114    class PioSlavePort : public QueuedSlavePort
115    {
116      private:
117        SlavePacketQueue queue;
118
119      public:
120        PioSlavePort(const std::string &_name, RubyPort *_port);
121
122      protected:
123        bool recvTimingReq(PacketPtr pkt);
124
125        Tick recvAtomic(PacketPtr pkt)
126        { panic("recvAtomic not supported with ruby!"); }
127
128        void recvFunctional(PacketPtr pkt)
129        { panic("recvFunctional should never be called on pio slave port!"); }
130
131        AddrRangeList getAddrRanges() const;
132    };
133
134    struct SenderState : public Packet::SenderState
135    {
136        MemSlavePort *port;
137        SenderState(MemSlavePort * _port) : port(_port)
138        {}
139     };
140
141    typedef RubyPortParams Params;
142    RubyPort(const Params *p);
143    virtual ~RubyPort() {}
144
145    void init();
146
147    BaseMasterPort &getMasterPort(const std::string &if_name,
148                                  PortID idx = InvalidPortID);
149    BaseSlavePort &getSlavePort(const std::string &if_name,
150                                PortID idx = InvalidPortID);
151
152    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
153    virtual int outstandingCount() const = 0;
154    virtual bool isDeadlockEventScheduled() const = 0;
155    virtual void descheduleDeadlockEvent() = 0;
156
157    //
158    // Called by the controller to give the sequencer a pointer.
159    // A pointer to the controller is needed for atomic support.
160    //
161    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
162    uint32_t getId() { return m_version; }
163    unsigned int drain(DrainManager *dm);
164
165  protected:
166    void ruby_hit_callback(PacketPtr pkt);
167    void testDrainComplete();
168    void ruby_eviction_callback(const Address& address);
169
170    /**
171     * Called by the PIO port when receiving a timing response.
172     *
173     * @param pkt Response packet
174     * @param master_port_id Port id of the PIO port
175     *
176     * @return Whether successfully sent
177     */
178    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
179
180    uint32_t m_version;
181    AbstractController* m_controller;
182    MessageBuffer* m_mandatory_q_ptr;
183    bool m_usingRubyTester;
184    System* system;
185
186  private:
187    void addToRetryList(MemSlavePort * port)
188    {
189        assert(std::find(retryList.begin(), retryList.end(), port) ==
190               retryList.end());
191        retryList.push_back(port);
192    }
193
194    unsigned int getChildDrainCount(DrainManager *dm);
195
196    PioMasterPort pioMasterPort;
197    PioSlavePort pioSlavePort;
198    MemMasterPort memMasterPort;
199    MemSlavePort memSlavePort;
200    unsigned int gotAddrRanges;
201
202    /** Vector of M5 Ports attached to this Ruby port. */
203    typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
204    std::vector<MemSlavePort *> slave_ports;
205    std::vector<PioMasterPort *> master_ports;
206
207    DrainManager *drainManager;
208
209    //
210    // Based on similar code in the M5 bus.  Stores pointers to those ports
211    // that should be called when the Sequencer becomes available after a stall.
212    //
213    std::vector<MemSlavePort *> retryList;
214};
215
216#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
217