RubyPort.hh revision 10089
16876Ssteve.reinhardt@amd.com/* 210089Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427039Snate@binkert.org#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 437039Snate@binkert.org#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 446285Snate@binkert.org 457039Snate@binkert.org#include <cassert> 466285Snate@binkert.org#include <string> 476285Snate@binkert.org 486922SBrad.Beckmann@amd.com#include "mem/protocol/RequestStatus.hh" 499508Snilay@cs.wisc.edu#include "mem/ruby/buffers/MessageBuffer.hh" 507909Shestness@cs.utexas.edu#include "mem/ruby/system/System.hh" 518229Snate@binkert.org#include "mem/mem_object.hh" 528229Snate@binkert.org#include "mem/physical.hh" 537039Snate@binkert.org#include "mem/tport.hh" 546876Ssteve.reinhardt@amd.com#include "params/RubyPort.hh" 556876Ssteve.reinhardt@amd.com 566876Ssteve.reinhardt@amd.comclass AbstractController; 576876Ssteve.reinhardt@amd.com 587039Snate@binkert.orgclass RubyPort : public MemObject 597039Snate@binkert.org{ 607039Snate@binkert.org public: 618922Swilliam.wang@arm.com class M5Port : public QueuedSlavePort 626882SBrad.Beckmann@amd.com { 637039Snate@binkert.org private: 648914Sandreas.hansson@arm.com 658975Sandreas.hansson@arm.com SlavePacketQueue queue; 666882SBrad.Beckmann@amd.com RubyPort *ruby_port; 678436SBrad.Beckmann@amd.com RubySystem* ruby_system; 687915SBrad.Beckmann@amd.com bool access_phys_mem; 696882SBrad.Beckmann@amd.com 706882SBrad.Beckmann@amd.com public: 717915SBrad.Beckmann@amd.com M5Port(const std::string &_name, RubyPort *_port, 7210089Sandreas.hansson@arm.com RubySystem*_system, bool _access_phys_mem, PortID id); 736882SBrad.Beckmann@amd.com void hitCallback(PacketPtr pkt); 748717Snilay@cs.wisc.edu void evictionCallback(const Address& address); 756882SBrad.Beckmann@amd.com 766882SBrad.Beckmann@amd.com protected: 7710089Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 7810089Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 7910089Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 8010089Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 816882SBrad.Beckmann@amd.com 826882SBrad.Beckmann@amd.com private: 8310089Sandreas.hansson@arm.com bool isPhysMemAddress(Addr addr) const; 846882SBrad.Beckmann@amd.com }; 856882SBrad.Beckmann@amd.com 868922Swilliam.wang@arm.com class PioPort : public QueuedMasterPort 876882SBrad.Beckmann@amd.com { 887039Snate@binkert.org private: 898914Sandreas.hansson@arm.com 908975Sandreas.hansson@arm.com MasterPacketQueue queue; 9110089Sandreas.hansson@arm.com RubyPort *ruby_port; 928914Sandreas.hansson@arm.com 936882SBrad.Beckmann@amd.com public: 947039Snate@binkert.org PioPort(const std::string &_name, RubyPort *_port); 956882SBrad.Beckmann@amd.com 966882SBrad.Beckmann@amd.com protected: 9710089Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 9810089Sandreas.hansson@arm.com { return ruby_port->recvTimingResp(pkt, id); } 996882SBrad.Beckmann@amd.com }; 1006882SBrad.Beckmann@amd.com 1016876Ssteve.reinhardt@amd.com typedef RubyPortParams Params; 1026876Ssteve.reinhardt@amd.com RubyPort(const Params *p); 1036882SBrad.Beckmann@amd.com virtual ~RubyPort() {} 1046882SBrad.Beckmann@amd.com 1056882SBrad.Beckmann@amd.com void init(); 1066285Snate@binkert.org 1079294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1089294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1099294Sandreas.hansson@arm.com BaseSlavePort &getSlavePort(const std::string &if_name, 1109294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1116876Ssteve.reinhardt@amd.com 1128615Snilay@cs.wisc.edu virtual RequestStatus makeRequest(PacketPtr pkt) = 0; 1138688Snilay@cs.wisc.edu virtual int outstandingCount() const = 0; 1148688Snilay@cs.wisc.edu virtual bool isDeadlockEventScheduled() const = 0; 1158688Snilay@cs.wisc.edu virtual void descheduleDeadlockEvent() = 0; 1166882SBrad.Beckmann@amd.com 1176882SBrad.Beckmann@amd.com // 1186882SBrad.Beckmann@amd.com // Called by the controller to give the sequencer a pointer. 1196882SBrad.Beckmann@amd.com // A pointer to the controller is needed for atomic support. 1206882SBrad.Beckmann@amd.com // 1216882SBrad.Beckmann@amd.com void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 12210012Snilay@cs.wisc.edu uint32_t getId() { return m_version; } 1239342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 1246285Snate@binkert.org 1257039Snate@binkert.org protected: 1267055Snate@binkert.org const std::string m_name; 1277039Snate@binkert.org void ruby_hit_callback(PacketPtr pkt); 1288688Snilay@cs.wisc.edu void testDrainComplete(); 1298717Snilay@cs.wisc.edu void ruby_eviction_callback(const Address& address); 1306285Snate@binkert.org 13110089Sandreas.hansson@arm.com /** 13210089Sandreas.hansson@arm.com * Called by the PIO port when receiving a timing response. 13310089Sandreas.hansson@arm.com * 13410089Sandreas.hansson@arm.com * @param pkt Response packet 13510089Sandreas.hansson@arm.com * @param master_port_id Port id of the PIO port 13610089Sandreas.hansson@arm.com * 13710089Sandreas.hansson@arm.com * @return Whether successfully sent 13810089Sandreas.hansson@arm.com */ 13910089Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 14010089Sandreas.hansson@arm.com 14110012Snilay@cs.wisc.edu uint32_t m_version; 1427039Snate@binkert.org AbstractController* m_controller; 1437039Snate@binkert.org MessageBuffer* m_mandatory_q_ptr; 1448851Sandreas.hansson@arm.com PioPort pio_port; 1457910SBrad.Beckmann@amd.com bool m_usingRubyTester; 1466876Ssteve.reinhardt@amd.com 1477039Snate@binkert.org private: 1487910SBrad.Beckmann@amd.com void addToRetryList(M5Port * port) 1497910SBrad.Beckmann@amd.com { 15010089Sandreas.hansson@arm.com assert(std::find(retryList.begin(), retryList.end(), port) == 15110089Sandreas.hansson@arm.com retryList.end()); 15210089Sandreas.hansson@arm.com retryList.push_back(port); 1537910SBrad.Beckmann@amd.com } 1547910SBrad.Beckmann@amd.com 1559342SAndreas.Sandberg@arm.com unsigned int getChildDrainCount(DrainManager *dm); 1568688Snilay@cs.wisc.edu 1578922Swilliam.wang@arm.com /** Vector of M5 Ports attached to this Ruby port. */ 1588686Snilay@cs.wisc.edu typedef std::vector<M5Port*>::iterator CpuPortIter; 1598922Swilliam.wang@arm.com std::vector<M5Port*> slave_ports; 1608922Swilliam.wang@arm.com std::vector<PioPort*> master_ports; 1618686Snilay@cs.wisc.edu 1629342SAndreas.Sandberg@arm.com DrainManager *drainManager; 1638688Snilay@cs.wisc.edu 1648436SBrad.Beckmann@amd.com RubySystem* ruby_system; 1658923Sandreas.hansson@arm.com System* system; 1667910SBrad.Beckmann@amd.com 1677910SBrad.Beckmann@amd.com // 1687910SBrad.Beckmann@amd.com // Based on similar code in the M5 bus. Stores pointers to those ports 1697910SBrad.Beckmann@amd.com // that should be called when the Sequencer becomes available after a stall. 1707910SBrad.Beckmann@amd.com // 17110089Sandreas.hansson@arm.com std::vector<M5Port*> retryList; 1727910SBrad.Beckmann@amd.com 1737915SBrad.Beckmann@amd.com bool access_phys_mem; 1746285Snate@binkert.org}; 1756285Snate@binkert.org 1767039Snate@binkert.org#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 177