RubyPort.cc revision 8949
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Ruby.hh" 45#include "mem/protocol/AccessPermission.hh" 46#include "mem/ruby/slicc_interface/AbstractController.hh" 47#include "mem/ruby/system/RubyPort.hh" 48#include "sim/system.hh" 49 50RubyPort::RubyPort(const Params *p) 51 : MemObject(p), m_version(p->version), m_controller(NULL), 52 m_mandatory_q_ptr(NULL), 53 pio_port(csprintf("%s-pio-port", name()), this), 54 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 55 drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), 56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 57{ 58 assert(m_version != -1); 59 60 // create the slave ports based on the number of connected ports 61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 63 this, ruby_system, access_phys_mem)); 64 } 65 66 // create the master ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 68 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 69 this)); 70 } 71} 72 73void 74RubyPort::init() 75{ 76 assert(m_controller != NULL); 77 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 78} 79 80MasterPort & 81RubyPort::getMasterPort(const std::string &if_name, int idx) 82{ 83 if (if_name == "pio_port") { 84 return pio_port; 85 } 86 87 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 88 // port 89 if (if_name != "master") { 90 // pass it along to our super class 91 return MemObject::getMasterPort(if_name, idx); 92 } else { 93 if (idx >= static_cast<int>(master_ports.size())) { 94 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 95 } 96 97 return *master_ports[idx]; 98 } 99} 100 101SlavePort & 102RubyPort::getSlavePort(const std::string &if_name, int idx) 103{ 104 // used by the CPUs to connect the caches to the interconnect, and 105 // for the x86 case also the interrupt master 106 if (if_name != "slave") { 107 // pass it along to our super class 108 return MemObject::getSlavePort(if_name, idx); 109 } else { 110 if (idx >= static_cast<int>(slave_ports.size())) { 111 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 112 } 113 114 return *slave_ports[idx]; 115 } 116} 117 118RubyPort::PioPort::PioPort(const std::string &_name, 119 RubyPort *_port) 120 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 121 ruby_port(_port) 122{ 123 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 124} 125 126RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 127 RubySystem *_system, bool _access_phys_mem) 128 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 129 ruby_port(_port), ruby_system(_system), 130 _onRetryList(false), access_phys_mem(_access_phys_mem) 131{ 132 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 133} 134 135Tick 136RubyPort::M5Port::recvAtomic(PacketPtr pkt) 137{ 138 panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 139 return 0; 140} 141 142 143bool 144RubyPort::PioPort::recvTiming(PacketPtr pkt) 145{ 146 // In FS mode, ruby memory will receive pio responses from devices 147 // and it must forward these responses back to the particular CPU. 148 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 149 150 assert(pkt->isResponse()); 151 152 // First we must retrieve the request port from the sender State 153 RubyPort::SenderState *senderState = 154 safe_cast<RubyPort::SenderState *>(pkt->senderState); 155 M5Port *port = senderState->port; 156 assert(port != NULL); 157 158 // pop the sender state from the packet 159 pkt->senderState = senderState->saved; 160 delete senderState; 161 162 port->sendTiming(pkt); 163 164 return true; 165} 166 167bool 168RubyPort::M5Port::recvTiming(PacketPtr pkt) 169{ 170 DPRINTF(RubyPort, 171 "Timing access caught for address %#x\n", pkt->getAddr()); 172 173 //dsm: based on SimpleTimingPort::recvTiming(pkt); 174 175 // The received packets should only be M5 requests, which should never 176 // get nacked. There used to be code to hanldle nacks here, but 177 // I'm pretty sure it didn't work correctly with the drain code, 178 // so that would need to be fixed if we ever added it back. 179 assert(pkt->isRequest()); 180 181 if (pkt->memInhibitAsserted()) { 182 warn("memInhibitAsserted???"); 183 // snooper will supply based on copy of packet 184 // still target's responsibility to delete packet 185 delete pkt; 186 return true; 187 } 188 189 // Save the port in the sender state object to be used later to 190 // route the response 191 pkt->senderState = new SenderState(this, pkt->senderState); 192 193 // Check for pio requests and directly send them to the dedicated 194 // pio port. 195 if (!isPhysMemAddress(pkt->getAddr())) { 196 assert(ruby_port->pio_port.isConnected()); 197 DPRINTF(RubyPort, 198 "Request for address 0x%#x is assumed to be a pio request\n", 199 pkt->getAddr()); 200 201 return ruby_port->pio_port.sendNextCycle(pkt); 202 } 203 204 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 205 RubySystem::getBlockSizeBytes()); 206 207 // Submit the ruby request 208 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 209 210 // If the request successfully issued then we should return true. 211 // Otherwise, we need to delete the senderStatus we just created and return 212 // false. 213 if (requestStatus == RequestStatus_Issued) { 214 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 215 return true; 216 } 217 218 // 219 // Unless one is using the ruby tester, record the stalled M5 port for 220 // later retry when the sequencer becomes free. 221 // 222 if (!ruby_port->m_usingRubyTester) { 223 ruby_port->addToRetryList(this); 224 } 225 226 DPRINTF(RubyPort, 227 "Request for address %#x did not issue because %s\n", 228 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 229 230 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 231 pkt->senderState = senderState->saved; 232 delete senderState; 233 return false; 234} 235 236bool 237RubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 238{ 239 Address address(pkt->getAddr()); 240 Address line_address(address); 241 line_address.makeLineAddress(); 242 243 AccessPermission access_perm = AccessPermission_NotPresent; 244 int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 245 246 DPRINTF(RubyPort, "Functional Read request for %s\n",address); 247 248 unsigned int num_ro = 0; 249 unsigned int num_rw = 0; 250 unsigned int num_busy = 0; 251 unsigned int num_backing_store = 0; 252 unsigned int num_invalid = 0; 253 254 // In this loop we count the number of controllers that have the given 255 // address in read only, read write and busy states. 256 for (int i = 0; i < num_controllers; ++i) { 257 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 258 getAccessPermission(line_address); 259 if (access_perm == AccessPermission_Read_Only) 260 num_ro++; 261 else if (access_perm == AccessPermission_Read_Write) 262 num_rw++; 263 else if (access_perm == AccessPermission_Busy) 264 num_busy++; 265 else if (access_perm == AccessPermission_Backing_Store) 266 // See RubySlicc_Exports.sm for details, but Backing_Store is meant 267 // to represent blocks in memory *for Broadcast/Snooping protocols*, 268 // where memory has no idea whether it has an exclusive copy of data 269 // or not. 270 num_backing_store++; 271 else if (access_perm == AccessPermission_Invalid || 272 access_perm == AccessPermission_NotPresent) 273 num_invalid++; 274 } 275 assert(num_rw <= 1); 276 277 uint8* data = pkt->getPtr<uint8_t>(true); 278 unsigned int size_in_bytes = pkt->getSize(); 279 unsigned startByte = address.getAddress() - line_address.getAddress(); 280 281 // This if case is meant to capture what happens in a Broadcast/Snoop 282 // protocol where the block does not exist in the cache hierarchy. You 283 // only want to read from the Backing_Store memory if there is no copy in 284 // the cache hierarchy, otherwise you want to try to read the RO or RW 285 // copies existing in the cache hierarchy (covered by the else statement). 286 // The reason is because the Backing_Store memory could easily be stale, if 287 // there are copies floating around the cache hierarchy, so you want to read 288 // it only if it's not in the cache hierarchy at all. 289 if (num_invalid == (num_controllers - 1) && 290 num_backing_store == 1) 291 { 292 DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 293 for (int i = 0; i < num_controllers; ++i) { 294 access_perm = ruby_system->m_abs_cntrl_vec[i] 295 ->getAccessPermission(line_address); 296 if (access_perm == AccessPermission_Backing_Store) { 297 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 298 ->getDataBlock(line_address); 299 300 DPRINTF(RubyPort, "reading from %s block %s\n", 301 ruby_system->m_abs_cntrl_vec[i]->name(), block); 302 for (unsigned i = 0; i < size_in_bytes; ++i) { 303 data[i] = block.getByte(i + startByte); 304 } 305 return true; 306 } 307 } 308 } else { 309 // In Broadcast/Snoop protocols, this covers if you know the block 310 // exists somewhere in the caching hierarchy, then you want to read any 311 // valid RO or RW block. In directory protocols, same thing, you want 312 // to read any valid readable copy of the block. 313 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 314 num_busy, num_ro, num_rw); 315 // In this loop, we try to figure which controller has a read only or 316 // a read write copy of the given address. Any valid copy would suffice 317 // for a functional read. 318 for(int i = 0;i < num_controllers;++i) { 319 access_perm = ruby_system->m_abs_cntrl_vec[i] 320 ->getAccessPermission(line_address); 321 if(access_perm == AccessPermission_Read_Only || 322 access_perm == AccessPermission_Read_Write) 323 { 324 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 325 ->getDataBlock(line_address); 326 327 DPRINTF(RubyPort, "reading from %s block %s\n", 328 ruby_system->m_abs_cntrl_vec[i]->name(), block); 329 for (unsigned i = 0; i < size_in_bytes; ++i) { 330 data[i] = block.getByte(i + startByte); 331 } 332 return true; 333 } 334 } 335 } 336 return false; 337} 338 339bool 340RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 341{ 342 Address addr(pkt->getAddr()); 343 Address line_addr = line_address(addr); 344 AccessPermission access_perm = AccessPermission_NotPresent; 345 int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 346 347 DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 348 349 unsigned int num_ro = 0; 350 unsigned int num_rw = 0; 351 unsigned int num_busy = 0; 352 unsigned int num_backing_store = 0; 353 unsigned int num_invalid = 0; 354 355 // In this loop we count the number of controllers that have the given 356 // address in read only, read write and busy states. 357 for(int i = 0;i < num_controllers;++i) { 358 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 359 getAccessPermission(line_addr); 360 if (access_perm == AccessPermission_Read_Only) 361 num_ro++; 362 else if (access_perm == AccessPermission_Read_Write) 363 num_rw++; 364 else if (access_perm == AccessPermission_Busy) 365 num_busy++; 366 else if (access_perm == AccessPermission_Backing_Store) 367 // See RubySlicc_Exports.sm for details, but Backing_Store is meant 368 // to represent blocks in memory *for Broadcast/Snooping protocols*, 369 // where memory has no idea whether it has an exclusive copy of data 370 // or not. 371 num_backing_store++; 372 else if (access_perm == AccessPermission_Invalid || 373 access_perm == AccessPermission_NotPresent) 374 num_invalid++; 375 } 376 377 // If the number of read write copies is more than 1, then there is bug in 378 // coherence protocol. Otherwise, if all copies are in stable states, i.e. 379 // num_busy == 0, we update all the copies. If there is at least one copy 380 // in busy state, then we check if there is read write copy. If yes, then 381 // also we let the access go through. Or, if there is no copy in the cache 382 // hierarchy at all, we still want to do the write to the memory 383 // (Backing_Store) instead of failing. 384 385 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 386 num_busy, num_ro, num_rw); 387 assert(num_rw <= 1); 388 389 uint8* data = pkt->getPtr<uint8_t>(true); 390 unsigned int size_in_bytes = pkt->getSize(); 391 unsigned startByte = addr.getAddress() - line_addr.getAddress(); 392 393 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 394 (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 395 { 396 for(int i = 0; i < num_controllers;++i) { 397 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 398 getAccessPermission(line_addr); 399 if(access_perm == AccessPermission_Read_Only || 400 access_perm == AccessPermission_Read_Write|| 401 access_perm == AccessPermission_Maybe_Stale || 402 access_perm == AccessPermission_Backing_Store) 403 { 404 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 405 ->getDataBlock(line_addr); 406 407 DPRINTF(RubyPort, "%s\n",block); 408 for (unsigned i = 0; i < size_in_bytes; ++i) { 409 block.setByte(i + startByte, data[i]); 410 } 411 DPRINTF(RubyPort, "%s\n",block); 412 } 413 } 414 return true; 415 } 416 return false; 417} 418 419void 420RubyPort::M5Port::recvFunctional(PacketPtr pkt) 421{ 422 DPRINTF(RubyPort, "Functional access caught for address %#x\n", 423 pkt->getAddr()); 424 425 // Check for pio requests and directly send them to the dedicated 426 // pio port. 427 if (!isPhysMemAddress(pkt->getAddr())) { 428 assert(ruby_port->pio_port.isConnected()); 429 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 430 pkt->getAddr()); 431 panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 432 } 433 434 assert(pkt->getAddr() + pkt->getSize() <= 435 line_address(Address(pkt->getAddr())).getAddress() + 436 RubySystem::getBlockSizeBytes()); 437 438 bool accessSucceeded = false; 439 bool needsResponse = pkt->needsResponse(); 440 441 // Do the functional access on ruby memory 442 if (pkt->isRead()) { 443 accessSucceeded = doFunctionalRead(pkt); 444 } else if (pkt->isWrite()) { 445 accessSucceeded = doFunctionalWrite(pkt); 446 } else { 447 panic("RubyPort: unsupported functional command %s\n", 448 pkt->cmdString()); 449 } 450 451 // Unless the requester explicitly said otherwise, generate an error if 452 // the functional request failed 453 if (!accessSucceeded && !pkt->suppressFuncError()) { 454 fatal("Ruby functional %s failed for address %#x\n", 455 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 456 } 457 458 if (access_phys_mem) { 459 // The attached physmem contains the official version of data. 460 // The following command performs the real functional access. 461 // This line should be removed once Ruby supplies the official version 462 // of data. 463 ruby_port->system->getPhysMem().functionalAccess(pkt); 464 } 465 466 // turn packet around to go back to requester if response expected 467 if (needsResponse) { 468 pkt->setFunctionalResponseStatus(accessSucceeded); 469 470 // @todo There should not be a reverse call since the response is 471 // communicated through the packet pointer 472 // DPRINTF(RubyPort, "Sending packet back over port\n"); 473 // sendFunctional(pkt); 474 } 475 DPRINTF(RubyPort, "Functional access %s!\n", 476 accessSucceeded ? "successful":"failed"); 477} 478 479void 480RubyPort::ruby_hit_callback(PacketPtr pkt) 481{ 482 // Retrieve the request port from the sender State 483 RubyPort::SenderState *senderState = 484 safe_cast<RubyPort::SenderState *>(pkt->senderState); 485 M5Port *port = senderState->port; 486 assert(port != NULL); 487 488 // pop the sender state from the packet 489 pkt->senderState = senderState->saved; 490 delete senderState; 491 492 port->hitCallback(pkt); 493 494 // 495 // If we had to stall the M5Ports, wake them up because the sequencer 496 // likely has free resources now. 497 // 498 if (waitingOnSequencer) { 499 // 500 // Record the current list of ports to retry on a temporary list before 501 // calling sendRetry on those ports. sendRetry will cause an 502 // immediate retry, which may result in the ports being put back on the 503 // list. Therefore we want to clear the retryList before calling 504 // sendRetry. 505 // 506 std::list<M5Port*> curRetryList(retryList); 507 508 retryList.clear(); 509 waitingOnSequencer = false; 510 511 for (std::list<M5Port*>::iterator i = curRetryList.begin(); 512 i != curRetryList.end(); ++i) { 513 DPRINTF(RubyPort, 514 "Sequencer may now be free. SendRetry to port %s\n", 515 (*i)->name()); 516 (*i)->onRetryList(false); 517 (*i)->sendRetry(); 518 } 519 } 520 521 testDrainComplete(); 522} 523 524void 525RubyPort::testDrainComplete() 526{ 527 //If we weren't able to drain before, we might be able to now. 528 if (drainEvent != NULL) { 529 unsigned int drainCount = getDrainCount(drainEvent); 530 DPRINTF(Config, "Drain count: %u\n", drainCount); 531 if (drainCount == 0) { 532 drainEvent->process(); 533 // Clear the drain event once we're done with it. 534 drainEvent = NULL; 535 } 536 } 537} 538 539unsigned int 540RubyPort::getDrainCount(Event *de) 541{ 542 int count = 0; 543 // 544 // If the sequencer is not empty, then requests need to drain. 545 // The outstandingCount is the number of requests outstanding and thus the 546 // number of times M5's timing port will process the drain event. 547 // 548 count += outstandingCount(); 549 550 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 551 552 // To simplify the draining process, the sequencer's deadlock detection 553 // event should have been descheduled. 554 assert(isDeadlockEventScheduled() == false); 555 556 if (pio_port.isConnected()) { 557 count += pio_port.drain(de); 558 DPRINTF(Config, "count after pio check %d\n", count); 559 } 560 561 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 562 count += (*p)->drain(de); 563 DPRINTF(Config, "count after slave port check %d\n", count); 564 } 565 566 for (std::vector<PioPort*>::iterator p = master_ports.begin(); 567 p != master_ports.end(); ++p) { 568 count += (*p)->drain(de); 569 DPRINTF(Config, "count after master port check %d\n", count); 570 } 571 572 DPRINTF(Config, "final count %d\n", count); 573 574 return count; 575} 576 577unsigned int 578RubyPort::drain(Event *de) 579{ 580 if (isDeadlockEventScheduled()) { 581 descheduleDeadlockEvent(); 582 } 583 584 int count = getDrainCount(de); 585 586 // Set status 587 if (count != 0) { 588 drainEvent = de; 589 590 changeState(SimObject::Draining); 591 return count; 592 } 593 594 changeState(SimObject::Drained); 595 return 0; 596} 597 598void 599RubyPort::M5Port::hitCallback(PacketPtr pkt) 600{ 601 bool needsResponse = pkt->needsResponse(); 602 603 // 604 // Unless specified at configuraiton, all responses except failed SC 605 // and Flush operations access M5 physical memory. 606 // 607 bool accessPhysMem = access_phys_mem; 608 609 if (pkt->isLLSC()) { 610 if (pkt->isWrite()) { 611 if (pkt->req->getExtraData() != 0) { 612 // 613 // Successful SC packets convert to normal writes 614 // 615 pkt->convertScToWrite(); 616 } else { 617 // 618 // Failed SC packets don't access physical memory and thus 619 // the RubyPort itself must convert it to a response. 620 // 621 accessPhysMem = false; 622 } 623 } else { 624 // 625 // All LL packets convert to normal loads so that M5 PhysMem does 626 // not lock the blocks. 627 // 628 pkt->convertLlToRead(); 629 } 630 } 631 632 // 633 // Flush requests don't access physical memory 634 // 635 if (pkt->isFlush()) { 636 accessPhysMem = false; 637 } 638 639 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 640 641 if (accessPhysMem) { 642 ruby_port->system->getPhysMem().access(pkt); 643 } else if (needsResponse) { 644 pkt->makeResponse(); 645 } 646 647 // turn packet around to go back to requester if response expected 648 if (needsResponse) { 649 DPRINTF(RubyPort, "Sending packet back over port\n"); 650 sendNextCycle(pkt); 651 } else { 652 delete pkt; 653 } 654 DPRINTF(RubyPort, "Hit callback done!\n"); 655} 656 657bool 658RubyPort::M5Port::sendNextCycle(PacketPtr pkt, bool send_as_snoop) 659{ 660 //minimum latency, must be > 0 661 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()), 662 send_as_snoop); 663 return true; 664} 665 666bool 667RubyPort::PioPort::sendNextCycle(PacketPtr pkt) 668{ 669 //minimum latency, must be > 0 670 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 671 return true; 672} 673 674AddrRangeList 675RubyPort::M5Port::getAddrRanges() 676{ 677 // at the moment the assumption is that the master does not care 678 AddrRangeList ranges; 679 return ranges; 680} 681 682bool 683RubyPort::M5Port::isPhysMemAddress(Addr addr) 684{ 685 return ruby_port->system->isMemAddr(addr); 686} 687 688unsigned 689RubyPort::M5Port::deviceBlockSize() const 690{ 691 return (unsigned) RubySystem::getBlockSizeBytes(); 692} 693 694void 695RubyPort::ruby_eviction_callback(const Address& address) 696{ 697 DPRINTF(RubyPort, "Sending invalidations.\n"); 698 // should this really be using funcMasterId? 699 Request req(address.getAddress(), 0, 0, Request::funcMasterId); 700 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 701 if ((*p)->getMasterPort().isSnooping()) { 702 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq); 703 // send as a snoop request 704 (*p)->sendNextCycle(pkt, true); 705 } 706 } 707} 708