RubyPort.cc revision 10961
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "mem/simple_mem.hh" 50#include "sim/full_system.hh" 51#include "sim/system.hh" 52 53RubyPort::RubyPort(const Params *p) 54 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), 55 m_controller(NULL), m_mandatory_q_ptr(NULL), 56 m_usingRubyTester(p->using_ruby_tester), system(p->system), 57 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 58 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 59 memMasterPort(csprintf("%s.mem-master-port", name()), this), 60 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 61 p->ruby_system->getAccessBackingStore(), -1), 62 gotAddrRanges(p->port_master_connection_count) 63{ 64 assert(m_version != -1); 65 66 // create the slave ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 68 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 69 i), this, p->ruby_system->getAccessBackingStore(), i)); 70 } 71 72 // create the master ports based on the number of connected ports 73 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 74 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 75 name(), i), this)); 76 } 77} 78 79void 80RubyPort::init() 81{ 82 assert(m_controller != NULL); 83 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 84 m_mandatory_q_ptr->setSender(this); 85} 86 87BaseMasterPort & 88RubyPort::getMasterPort(const std::string &if_name, PortID idx) 89{ 90 if (if_name == "mem_master_port") { 91 return memMasterPort; 92 } 93 94 if (if_name == "pio_master_port") { 95 return pioMasterPort; 96 } 97 98 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 99 // port 100 if (if_name != "master") { 101 // pass it along to our super class 102 return MemObject::getMasterPort(if_name, idx); 103 } else { 104 if (idx >= static_cast<PortID>(master_ports.size())) { 105 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 106 } 107 108 return *master_ports[idx]; 109 } 110} 111 112BaseSlavePort & 113RubyPort::getSlavePort(const std::string &if_name, PortID idx) 114{ 115 if (if_name == "mem_slave_port") { 116 return memSlavePort; 117 } 118 119 if (if_name == "pio_slave_port") 120 return pioSlavePort; 121 122 // used by the CPUs to connect the caches to the interconnect, and 123 // for the x86 case also the interrupt master 124 if (if_name != "slave") { 125 // pass it along to our super class 126 return MemObject::getSlavePort(if_name, idx); 127 } else { 128 if (idx >= static_cast<PortID>(slave_ports.size())) { 129 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 130 } 131 132 return *slave_ports[idx]; 133 } 134} 135 136RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 137 RubyPort *_port) 138 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 139 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 140{ 141 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 142} 143 144RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 145 RubyPort *_port) 146 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 147{ 148 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 149} 150 151RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 152 RubyPort *_port) 153 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 154 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 155{ 156 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 157} 158 159RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 160 bool _access_backing_store, PortID id) 161 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 162 access_backing_store(_access_backing_store) 163{ 164 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 165} 166 167bool 168RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 169{ 170 RubyPort *rp = static_cast<RubyPort *>(&owner); 171 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 172 173 // send next cycle 174 rp->pioSlavePort.schedTimingResp( 175 pkt, curTick() + rp->m_ruby_system->clockPeriod()); 176 return true; 177} 178 179bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 180{ 181 // got a response from a device 182 assert(pkt->isResponse()); 183 184 // First we must retrieve the request port from the sender State 185 RubyPort::SenderState *senderState = 186 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 187 MemSlavePort *port = senderState->port; 188 assert(port != NULL); 189 delete senderState; 190 191 // In FS mode, ruby memory will receive pio responses from devices 192 // and it must forward these responses back to the particular CPU. 193 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 194 pkt->getAddr(), port->name()); 195 196 // attempt to send the response in the next cycle 197 RubyPort *rp = static_cast<RubyPort *>(&owner); 198 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod()); 199 200 return true; 201} 202 203bool 204RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 205{ 206 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 207 208 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 209 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 210 for (auto it = l.begin(); it != l.end(); ++it) { 211 if (it->contains(pkt->getAddr())) { 212 // generally it is not safe to assume success here as 213 // the port could be blocked 214 bool M5_VAR_USED success = 215 ruby_port->master_ports[i]->sendTimingReq(pkt); 216 assert(success); 217 return true; 218 } 219 } 220 } 221 panic("Should never reach here!\n"); 222} 223 224bool 225RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 226{ 227 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 228 pkt->getAddr(), id); 229 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 230 231 if (pkt->memInhibitAsserted()) 232 panic("RubyPort should never see an inhibited request\n"); 233 234 // Check for pio requests and directly send them to the dedicated 235 // pio port. 236 if (!isPhysMemAddress(pkt->getAddr())) { 237 assert(ruby_port->memMasterPort.isConnected()); 238 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 239 pkt->getAddr()); 240 241 // Save the port in the sender state object to be used later to 242 // route the response 243 pkt->pushSenderState(new SenderState(this)); 244 245 // send next cycle 246 RubySystem *rs = ruby_port->m_ruby_system; 247 ruby_port->memMasterPort.schedTimingReq(pkt, 248 curTick() + rs->clockPeriod()); 249 return true; 250 } 251 252 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 253 RubySystem::getBlockSizeBytes()); 254 255 // Submit the ruby request 256 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 257 258 // If the request successfully issued then we should return true. 259 // Otherwise, we need to tell the port to retry at a later point 260 // and return false. 261 if (requestStatus == RequestStatus_Issued) { 262 // Save the port in the sender state object to be used later to 263 // route the response 264 pkt->pushSenderState(new SenderState(this)); 265 266 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 267 pkt->getAddr()); 268 return true; 269 } 270 271 // 272 // Unless one is using the ruby tester, record the stalled M5 port for 273 // later retry when the sequencer becomes free. 274 // 275 if (!ruby_port->m_usingRubyTester) { 276 ruby_port->addToRetryList(this); 277 } 278 279 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 280 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 281 282 return false; 283} 284 285void 286RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 287{ 288 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 289 290 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner); 291 RubySystem *rs = rp->m_ruby_system; 292 293 // Check for pio requests and directly send them to the dedicated 294 // pio port. 295 if (!isPhysMemAddress(pkt->getAddr())) { 296 assert(rp->memMasterPort.isConnected()); 297 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 298 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 299 } 300 301 assert(pkt->getAddr() + pkt->getSize() <= 302 line_address(Address(pkt->getAddr())).getAddress() + 303 RubySystem::getBlockSizeBytes()); 304 305 if (access_backing_store) { 306 // The attached physmem contains the official version of data. 307 // The following command performs the real functional access. 308 // This line should be removed once Ruby supplies the official version 309 // of data. 310 rs->getPhysMem()->functionalAccess(pkt); 311 } else { 312 bool accessSucceeded = false; 313 bool needsResponse = pkt->needsResponse(); 314 315 // Do the functional access on ruby memory 316 if (pkt->isRead()) { 317 accessSucceeded = rs->functionalRead(pkt); 318 } else if (pkt->isWrite()) { 319 accessSucceeded = rs->functionalWrite(pkt); 320 } else { 321 panic("Unsupported functional command %s\n", pkt->cmdString()); 322 } 323 324 // Unless the requester explicitly said otherwise, generate an error if 325 // the functional request failed 326 if (!accessSucceeded && !pkt->suppressFuncError()) { 327 fatal("Ruby functional %s failed for address %#x\n", 328 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 329 } 330 331 // turn packet around to go back to requester if response expected 332 if (needsResponse) { 333 pkt->setFunctionalResponseStatus(accessSucceeded); 334 } 335 336 DPRINTF(RubyPort, "Functional access %s!\n", 337 accessSucceeded ? "successful":"failed"); 338 } 339} 340 341void 342RubyPort::ruby_hit_callback(PacketPtr pkt) 343{ 344 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 345 pkt->getAddr()); 346 347 // The packet was destined for memory and has not yet been turned 348 // into a response 349 assert(system->isMemAddr(pkt->getAddr())); 350 assert(pkt->isRequest()); 351 352 // First we must retrieve the request port from the sender State 353 RubyPort::SenderState *senderState = 354 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 355 MemSlavePort *port = senderState->port; 356 assert(port != NULL); 357 delete senderState; 358 359 port->hitCallback(pkt); 360 361 // 362 // If we had to stall the MemSlavePorts, wake them up because the sequencer 363 // likely has free resources now. 364 // 365 if (!retryList.empty()) { 366 // 367 // Record the current list of ports to retry on a temporary list before 368 // calling sendRetry on those ports. sendRetry will cause an 369 // immediate retry, which may result in the ports being put back on the 370 // list. Therefore we want to clear the retryList before calling 371 // sendRetry. 372 // 373 std::vector<MemSlavePort *> curRetryList(retryList); 374 375 retryList.clear(); 376 377 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 378 DPRINTF(RubyPort, 379 "Sequencer may now be free. SendRetry to port %s\n", 380 (*i)->name()); 381 (*i)->sendRetryReq(); 382 } 383 } 384 385 testDrainComplete(); 386} 387 388void 389RubyPort::testDrainComplete() 390{ 391 //If we weren't able to drain before, we might be able to now. 392 if (drainState() == DrainState::Draining) { 393 unsigned int drainCount = outstandingCount(); 394 DPRINTF(Drain, "Drain count: %u\n", drainCount); 395 if (drainCount == 0) { 396 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 397 signalDrainDone(); 398 } 399 } 400} 401 402DrainState 403RubyPort::drain() 404{ 405 if (isDeadlockEventScheduled()) { 406 descheduleDeadlockEvent(); 407 } 408 409 // 410 // If the RubyPort is not empty, then it needs to clear all outstanding 411 // requests before it should call signalDrainDone() 412 // 413 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 414 if (outstandingCount() > 0) { 415 DPRINTF(Drain, "RubyPort not drained\n"); 416 return DrainState::Draining; 417 } else { 418 return DrainState::Drained; 419 } 420} 421 422void 423RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 424{ 425 bool needsResponse = pkt->needsResponse(); 426 427 // Unless specified at configuraiton, all responses except failed SC 428 // and Flush operations access M5 physical memory. 429 bool accessPhysMem = access_backing_store; 430 431 if (pkt->isLLSC()) { 432 if (pkt->isWrite()) { 433 if (pkt->req->getExtraData() != 0) { 434 // 435 // Successful SC packets convert to normal writes 436 // 437 pkt->convertScToWrite(); 438 } else { 439 // 440 // Failed SC packets don't access physical memory and thus 441 // the RubyPort itself must convert it to a response. 442 // 443 accessPhysMem = false; 444 } 445 } else { 446 // 447 // All LL packets convert to normal loads so that M5 PhysMem does 448 // not lock the blocks. 449 // 450 pkt->convertLlToRead(); 451 } 452 } 453 454 // Flush requests don't access physical memory 455 if (pkt->isFlush()) { 456 accessPhysMem = false; 457 } 458 459 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 460 461 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 462 RubySystem *rs = ruby_port->m_ruby_system; 463 if (accessPhysMem) { 464 rs->getPhysMem()->access(pkt); 465 } else if (needsResponse) { 466 pkt->makeResponse(); 467 } 468 469 // turn packet around to go back to requester if response expected 470 if (needsResponse) { 471 DPRINTF(RubyPort, "Sending packet back over port\n"); 472 // Send a response in the same cycle. There is no need to delay the 473 // response because the response latency is already incurred in the 474 // Ruby protocol. 475 schedTimingResp(pkt, curTick()); 476 } else { 477 delete pkt; 478 } 479 480 DPRINTF(RubyPort, "Hit callback done!\n"); 481} 482 483AddrRangeList 484RubyPort::PioSlavePort::getAddrRanges() const 485{ 486 // at the moment the assumption is that the master does not care 487 AddrRangeList ranges; 488 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 489 490 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 491 ranges.splice(ranges.begin(), 492 ruby_port->master_ports[i]->getAddrRanges()); 493 } 494 for (const auto M5_VAR_USED &r : ranges) 495 DPRINTF(RubyPort, "%s\n", r.to_string()); 496 return ranges; 497} 498 499bool 500RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 501{ 502 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 503 return ruby_port->system->isMemAddr(addr); 504} 505 506void 507RubyPort::ruby_eviction_callback(const Address& address) 508{ 509 DPRINTF(RubyPort, "Sending invalidations.\n"); 510 // This request is deleted in the stack-allocated packet destructor 511 // when this function exits 512 // TODO: should this really be using funcMasterId? 513 RequestPtr req = 514 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 515 // Use a single packet to signal all snooping ports of the invalidation. 516 // This assumes that snooping ports do NOT modify the packet/request 517 Packet pkt(req, MemCmd::InvalidateReq); 518 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 519 // check if the connected master port is snooping 520 if ((*p)->isSnooping()) { 521 // send as a snoop request 522 (*p)->sendTimingSnoopReq(&pkt); 523 } 524 } 525} 526 527void 528RubyPort::PioMasterPort::recvRangeChange() 529{ 530 RubyPort &r = static_cast<RubyPort &>(owner); 531 r.gotAddrRanges--; 532 if (r.gotAddrRanges == 0 && FullSystem) { 533 r.pioSlavePort.sendRangeChange(); 534 } 535} 536