RubyPort.cc revision 10886
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "mem/simple_mem.hh" 50#include "sim/full_system.hh" 51#include "sim/system.hh" 52 53RubyPort::RubyPort(const Params *p) 54 : MemObject(p), m_version(p->version), m_controller(NULL), 55 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 56 system(p->system), 57 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 58 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 59 memMasterPort(csprintf("%s.mem-master-port", name()), this), 60 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 61 p->ruby_system, p->ruby_system->getAccessBackingStore(), -1), 62 gotAddrRanges(p->port_master_connection_count), drainManager(NULL) 63{ 64 assert(m_version != -1); 65 66 // create the slave ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 68 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 69 i), this, p->ruby_system, 70 p->ruby_system->getAccessBackingStore(), i)); 71 } 72 73 // create the master ports based on the number of connected ports 74 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 75 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 76 name(), i), this)); 77 } 78} 79 80void 81RubyPort::init() 82{ 83 assert(m_controller != NULL); 84 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 85 m_mandatory_q_ptr->setSender(this); 86} 87 88BaseMasterPort & 89RubyPort::getMasterPort(const std::string &if_name, PortID idx) 90{ 91 if (if_name == "mem_master_port") { 92 return memMasterPort; 93 } 94 95 if (if_name == "pio_master_port") { 96 return pioMasterPort; 97 } 98 99 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 100 // port 101 if (if_name != "master") { 102 // pass it along to our super class 103 return MemObject::getMasterPort(if_name, idx); 104 } else { 105 if (idx >= static_cast<PortID>(master_ports.size())) { 106 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 107 } 108 109 return *master_ports[idx]; 110 } 111} 112 113BaseSlavePort & 114RubyPort::getSlavePort(const std::string &if_name, PortID idx) 115{ 116 if (if_name == "mem_slave_port") { 117 return memSlavePort; 118 } 119 120 if (if_name == "pio_slave_port") 121 return pioSlavePort; 122 123 // used by the CPUs to connect the caches to the interconnect, and 124 // for the x86 case also the interrupt master 125 if (if_name != "slave") { 126 // pass it along to our super class 127 return MemObject::getSlavePort(if_name, idx); 128 } else { 129 if (idx >= static_cast<PortID>(slave_ports.size())) { 130 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 131 } 132 133 return *slave_ports[idx]; 134 } 135} 136 137RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 138 RubyPort *_port) 139 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 140 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 141{ 142 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 143} 144 145RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 146 RubyPort *_port) 147 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 148{ 149 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 150} 151 152RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 153 RubyPort *_port) 154 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 155 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 156{ 157 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 158} 159 160RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 161 RubySystem *_system, 162 bool _access_backing_store, PortID id) 163 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 164 ruby_system(_system), access_backing_store(_access_backing_store) 165{ 166 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 167} 168 169bool 170RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 171{ 172 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 173 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 174 175 // send next cycle 176 ruby_port->pioSlavePort.schedTimingResp( 177 pkt, curTick() + g_system_ptr->clockPeriod()); 178 return true; 179} 180 181bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 182{ 183 // got a response from a device 184 assert(pkt->isResponse()); 185 186 // First we must retrieve the request port from the sender State 187 RubyPort::SenderState *senderState = 188 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 189 MemSlavePort *port = senderState->port; 190 assert(port != NULL); 191 delete senderState; 192 193 // In FS mode, ruby memory will receive pio responses from devices 194 // and it must forward these responses back to the particular CPU. 195 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 196 pkt->getAddr(), port->name()); 197 198 // attempt to send the response in the next cycle 199 port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 200 201 return true; 202} 203 204bool 205RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 206{ 207 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 208 209 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 210 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 211 for (auto it = l.begin(); it != l.end(); ++it) { 212 if (it->contains(pkt->getAddr())) { 213 // generally it is not safe to assume success here as 214 // the port could be blocked 215 bool M5_VAR_USED success = 216 ruby_port->master_ports[i]->sendTimingReq(pkt); 217 assert(success); 218 return true; 219 } 220 } 221 } 222 panic("Should never reach here!\n"); 223} 224 225bool 226RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 227{ 228 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 229 pkt->getAddr(), id); 230 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 231 232 if (pkt->memInhibitAsserted()) 233 panic("RubyPort should never see an inhibited request\n"); 234 235 // Check for pio requests and directly send them to the dedicated 236 // pio port. 237 if (!isPhysMemAddress(pkt->getAddr())) { 238 assert(ruby_port->memMasterPort.isConnected()); 239 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 240 pkt->getAddr()); 241 242 // Save the port in the sender state object to be used later to 243 // route the response 244 pkt->pushSenderState(new SenderState(this)); 245 246 // send next cycle 247 ruby_port->memMasterPort.schedTimingReq(pkt, 248 curTick() + g_system_ptr->clockPeriod()); 249 return true; 250 } 251 252 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 253 RubySystem::getBlockSizeBytes()); 254 255 // Submit the ruby request 256 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 257 258 // If the request successfully issued then we should return true. 259 // Otherwise, we need to tell the port to retry at a later point 260 // and return false. 261 if (requestStatus == RequestStatus_Issued) { 262 // Save the port in the sender state object to be used later to 263 // route the response 264 pkt->pushSenderState(new SenderState(this)); 265 266 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 267 pkt->getAddr()); 268 return true; 269 } 270 271 // 272 // Unless one is using the ruby tester, record the stalled M5 port for 273 // later retry when the sequencer becomes free. 274 // 275 if (!ruby_port->m_usingRubyTester) { 276 ruby_port->addToRetryList(this); 277 } 278 279 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 280 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 281 282 return false; 283} 284 285void 286RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 287{ 288 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 289 290 // Check for pio requests and directly send them to the dedicated 291 // pio port. 292 if (!isPhysMemAddress(pkt->getAddr())) { 293 RubyPort *ruby_port M5_VAR_USED = static_cast<RubyPort *>(&owner); 294 assert(ruby_port->memMasterPort.isConnected()); 295 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 296 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 297 } 298 299 assert(pkt->getAddr() + pkt->getSize() <= 300 line_address(Address(pkt->getAddr())).getAddress() + 301 RubySystem::getBlockSizeBytes()); 302 303 if (access_backing_store) { 304 // The attached physmem contains the official version of data. 305 // The following command performs the real functional access. 306 // This line should be removed once Ruby supplies the official version 307 // of data. 308 ruby_system->getPhysMem()->functionalAccess(pkt); 309 } else { 310 bool accessSucceeded = false; 311 bool needsResponse = pkt->needsResponse(); 312 313 // Do the functional access on ruby memory 314 if (pkt->isRead()) { 315 accessSucceeded = ruby_system->functionalRead(pkt); 316 } else if (pkt->isWrite()) { 317 accessSucceeded = ruby_system->functionalWrite(pkt); 318 } else { 319 panic("Unsupported functional command %s\n", pkt->cmdString()); 320 } 321 322 // Unless the requester explicitly said otherwise, generate an error if 323 // the functional request failed 324 if (!accessSucceeded && !pkt->suppressFuncError()) { 325 fatal("Ruby functional %s failed for address %#x\n", 326 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 327 } 328 329 // turn packet around to go back to requester if response expected 330 if (needsResponse) { 331 pkt->setFunctionalResponseStatus(accessSucceeded); 332 } 333 334 DPRINTF(RubyPort, "Functional access %s!\n", 335 accessSucceeded ? "successful":"failed"); 336 } 337} 338 339void 340RubyPort::ruby_hit_callback(PacketPtr pkt) 341{ 342 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 343 pkt->getAddr()); 344 345 // The packet was destined for memory and has not yet been turned 346 // into a response 347 assert(system->isMemAddr(pkt->getAddr())); 348 assert(pkt->isRequest()); 349 350 // First we must retrieve the request port from the sender State 351 RubyPort::SenderState *senderState = 352 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 353 MemSlavePort *port = senderState->port; 354 assert(port != NULL); 355 delete senderState; 356 357 port->hitCallback(pkt); 358 359 // 360 // If we had to stall the MemSlavePorts, wake them up because the sequencer 361 // likely has free resources now. 362 // 363 if (!retryList.empty()) { 364 // 365 // Record the current list of ports to retry on a temporary list before 366 // calling sendRetry on those ports. sendRetry will cause an 367 // immediate retry, which may result in the ports being put back on the 368 // list. Therefore we want to clear the retryList before calling 369 // sendRetry. 370 // 371 std::vector<MemSlavePort *> curRetryList(retryList); 372 373 retryList.clear(); 374 375 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 376 DPRINTF(RubyPort, 377 "Sequencer may now be free. SendRetry to port %s\n", 378 (*i)->name()); 379 (*i)->sendRetryReq(); 380 } 381 } 382 383 testDrainComplete(); 384} 385 386void 387RubyPort::testDrainComplete() 388{ 389 //If we weren't able to drain before, we might be able to now. 390 if (drainManager != NULL) { 391 unsigned int drainCount = outstandingCount(); 392 DPRINTF(Drain, "Drain count: %u\n", drainCount); 393 if (drainCount == 0) { 394 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 395 drainManager->signalDrainDone(); 396 // Clear the drain manager once we're done with it. 397 drainManager = NULL; 398 } 399 } 400} 401 402unsigned int 403RubyPort::getChildDrainCount(DrainManager *dm) 404{ 405 int count = 0; 406 407 if (memMasterPort.isConnected()) { 408 count += memMasterPort.drain(dm); 409 DPRINTF(Config, "count after pio check %d\n", count); 410 } 411 412 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 413 count += (*p)->drain(dm); 414 DPRINTF(Config, "count after slave port check %d\n", count); 415 } 416 417 for (std::vector<PioMasterPort *>::iterator p = master_ports.begin(); 418 p != master_ports.end(); ++p) { 419 count += (*p)->drain(dm); 420 DPRINTF(Config, "count after master port check %d\n", count); 421 } 422 423 DPRINTF(Config, "final count %d\n", count); 424 return count; 425} 426 427unsigned int 428RubyPort::drain(DrainManager *dm) 429{ 430 if (isDeadlockEventScheduled()) { 431 descheduleDeadlockEvent(); 432 } 433 434 // 435 // If the RubyPort is not empty, then it needs to clear all outstanding 436 // requests before it should call drainManager->signalDrainDone() 437 // 438 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 439 bool need_drain = outstandingCount() > 0; 440 441 // 442 // Also, get the number of child ports that will also need to clear 443 // their buffered requests before they call drainManager->signalDrainDone() 444 // 445 unsigned int child_drain_count = getChildDrainCount(dm); 446 447 // Set status 448 if (need_drain) { 449 drainManager = dm; 450 451 DPRINTF(Drain, "RubyPort not drained\n"); 452 setDrainState(Drainable::Draining); 453 return child_drain_count + 1; 454 } 455 456 drainManager = NULL; 457 setDrainState(Drainable::Drained); 458 return child_drain_count; 459} 460 461void 462RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 463{ 464 bool needsResponse = pkt->needsResponse(); 465 466 // Unless specified at configuraiton, all responses except failed SC 467 // and Flush operations access M5 physical memory. 468 bool accessPhysMem = access_backing_store; 469 470 if (pkt->isLLSC()) { 471 if (pkt->isWrite()) { 472 if (pkt->req->getExtraData() != 0) { 473 // 474 // Successful SC packets convert to normal writes 475 // 476 pkt->convertScToWrite(); 477 } else { 478 // 479 // Failed SC packets don't access physical memory and thus 480 // the RubyPort itself must convert it to a response. 481 // 482 accessPhysMem = false; 483 } 484 } else { 485 // 486 // All LL packets convert to normal loads so that M5 PhysMem does 487 // not lock the blocks. 488 // 489 pkt->convertLlToRead(); 490 } 491 } 492 493 // Flush requests don't access physical memory 494 if (pkt->isFlush()) { 495 accessPhysMem = false; 496 } 497 498 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 499 500 if (accessPhysMem) { 501 ruby_system->getPhysMem()->access(pkt); 502 } else if (needsResponse) { 503 pkt->makeResponse(); 504 } 505 506 // turn packet around to go back to requester if response expected 507 if (needsResponse) { 508 DPRINTF(RubyPort, "Sending packet back over port\n"); 509 // send next cycle 510 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 511 } else { 512 delete pkt; 513 } 514 515 DPRINTF(RubyPort, "Hit callback done!\n"); 516} 517 518AddrRangeList 519RubyPort::PioSlavePort::getAddrRanges() const 520{ 521 // at the moment the assumption is that the master does not care 522 AddrRangeList ranges; 523 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 524 525 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 526 ranges.splice(ranges.begin(), 527 ruby_port->master_ports[i]->getAddrRanges()); 528 } 529 for (const auto M5_VAR_USED &r : ranges) 530 DPRINTF(RubyPort, "%s\n", r.to_string()); 531 return ranges; 532} 533 534bool 535RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 536{ 537 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 538 return ruby_port->system->isMemAddr(addr); 539} 540 541void 542RubyPort::ruby_eviction_callback(const Address& address) 543{ 544 DPRINTF(RubyPort, "Sending invalidations.\n"); 545 // This request is deleted in the stack-allocated packet destructor 546 // when this function exits 547 // TODO: should this really be using funcMasterId? 548 RequestPtr req = 549 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 550 // Use a single packet to signal all snooping ports of the invalidation. 551 // This assumes that snooping ports do NOT modify the packet/request 552 Packet pkt(req, MemCmd::InvalidateReq); 553 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 554 // check if the connected master port is snooping 555 if ((*p)->isSnooping()) { 556 // send as a snoop request 557 (*p)->sendTimingSnoopReq(&pkt); 558 } 559 } 560} 561 562void 563RubyPort::PioMasterPort::recvRangeChange() 564{ 565 RubyPort &r = static_cast<RubyPort &>(owner); 566 r.gotAddrRanges--; 567 if (r.gotAddrRanges == 0 && FullSystem) { 568 r.pioSlavePort.sendRangeChange(); 569 } 570} 571