RubyPort.cc revision 10467
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "sim/full_system.hh" 50#include "sim/system.hh" 51 52RubyPort::RubyPort(const Params *p) 53 : MemObject(p), m_version(p->version), m_controller(NULL), 54 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 55 system(p->system), 56 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 57 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 58 memMasterPort(csprintf("%s.mem-master-port", name()), this), 59 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 60 p->ruby_system, p->access_phys_mem, -1), 61 gotAddrRanges(p->port_master_connection_count), drainManager(NULL), 62 access_phys_mem(p->access_phys_mem) 63{ 64 assert(m_version != -1); 65 66 // create the slave ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 68 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 69 i), this, p->ruby_system, access_phys_mem, i)); 70 } 71 72 // create the master ports based on the number of connected ports 73 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 74 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 75 name(), i), this)); 76 } 77} 78 79void 80RubyPort::init() 81{ 82 assert(m_controller != NULL); 83 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 84 m_mandatory_q_ptr->setSender(this); 85} 86 87BaseMasterPort & 88RubyPort::getMasterPort(const std::string &if_name, PortID idx) 89{ 90 if (if_name == "mem_master_port") { 91 return memMasterPort; 92 } 93 94 if (if_name == "pio_master_port") { 95 return pioMasterPort; 96 } 97 98 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 99 // port 100 if (if_name != "master") { 101 // pass it along to our super class 102 return MemObject::getMasterPort(if_name, idx); 103 } else { 104 if (idx >= static_cast<PortID>(master_ports.size())) { 105 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 106 } 107 108 return *master_ports[idx]; 109 } 110} 111 112BaseSlavePort & 113RubyPort::getSlavePort(const std::string &if_name, PortID idx) 114{ 115 if (if_name == "mem_slave_port") { 116 return memSlavePort; 117 } 118 119 if (if_name == "pio_slave_port") 120 return pioSlavePort; 121 122 // used by the CPUs to connect the caches to the interconnect, and 123 // for the x86 case also the interrupt master 124 if (if_name != "slave") { 125 // pass it along to our super class 126 return MemObject::getSlavePort(if_name, idx); 127 } else { 128 if (idx >= static_cast<PortID>(slave_ports.size())) { 129 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 130 } 131 132 return *slave_ports[idx]; 133 } 134} 135 136RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 137 RubyPort *_port) 138 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 139{ 140 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 141} 142 143RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 144 RubyPort *_port) 145 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 146{ 147 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 148} 149 150RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 151 RubyPort *_port) 152 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 153{ 154 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 155} 156 157RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 158 RubySystem *_system, bool _access_phys_mem, PortID id) 159 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 160 ruby_system(_system), access_phys_mem(_access_phys_mem) 161{ 162 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 163} 164 165bool 166RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 167{ 168 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 169 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 170 171 // send next cycle 172 ruby_port->pioSlavePort.schedTimingResp( 173 pkt, curTick() + g_system_ptr->clockPeriod()); 174 return true; 175} 176 177bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 178{ 179 // got a response from a device 180 assert(pkt->isResponse()); 181 182 // In FS mode, ruby memory will receive pio responses from devices 183 // and it must forward these responses back to the particular CPU. 184 DPRINTF(RubyPort, "Pio response for address %#x, going to %d\n", 185 pkt->getAddr(), pkt->getDest()); 186 187 // First we must retrieve the request port from the sender State 188 RubyPort::SenderState *senderState = 189 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 190 MemSlavePort *port = senderState->port; 191 assert(port != NULL); 192 delete senderState; 193 194 // attempt to send the response in the next cycle 195 port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 196 197 return true; 198} 199 200bool 201RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 202{ 203 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 204 205 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 206 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 207 for (auto it = l.begin(); it != l.end(); ++it) { 208 if (it->contains(pkt->getAddr())) { 209 // generally it is not safe to assume success here as 210 // the port could be blocked 211 bool M5_VAR_USED success = 212 ruby_port->master_ports[i]->sendTimingReq(pkt); 213 assert(success); 214 return true; 215 } 216 } 217 } 218 panic("Should never reach here!\n"); 219} 220 221bool 222RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 223{ 224 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 225 pkt->getAddr(), id); 226 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 227 228 if (pkt->memInhibitAsserted()) 229 panic("RubyPort should never see an inhibited request\n"); 230 231 // Check for pio requests and directly send them to the dedicated 232 // pio port. 233 if (!isPhysMemAddress(pkt->getAddr())) { 234 assert(ruby_port->memMasterPort.isConnected()); 235 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 236 pkt->getAddr()); 237 238 // Save the port in the sender state object to be used later to 239 // route the response 240 pkt->pushSenderState(new SenderState(this)); 241 242 // send next cycle 243 ruby_port->memMasterPort.schedTimingReq(pkt, 244 curTick() + g_system_ptr->clockPeriod()); 245 return true; 246 } 247 248 // Save the port id to be used later to route the response 249 pkt->setSrc(id); 250 251 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 252 RubySystem::getBlockSizeBytes()); 253 254 // Submit the ruby request 255 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 256 257 // If the request successfully issued then we should return true. 258 // Otherwise, we need to tell the port to retry at a later point 259 // and return false. 260 if (requestStatus == RequestStatus_Issued) { 261 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 262 pkt->getAddr()); 263 return true; 264 } 265 266 // 267 // Unless one is using the ruby tester, record the stalled M5 port for 268 // later retry when the sequencer becomes free. 269 // 270 if (!ruby_port->m_usingRubyTester) { 271 ruby_port->addToRetryList(this); 272 } 273 274 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 275 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 276 277 return false; 278} 279 280void 281RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 282{ 283 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 284 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 285 286 // Check for pio requests and directly send them to the dedicated 287 // pio port. 288 if (!isPhysMemAddress(pkt->getAddr())) { 289 assert(ruby_port->memMasterPort.isConnected()); 290 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 291 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 292 } 293 294 assert(pkt->getAddr() + pkt->getSize() <= 295 line_address(Address(pkt->getAddr())).getAddress() + 296 RubySystem::getBlockSizeBytes()); 297 298 bool accessSucceeded = false; 299 bool needsResponse = pkt->needsResponse(); 300 301 // Do the functional access on ruby memory 302 if (pkt->isRead()) { 303 accessSucceeded = ruby_system->functionalRead(pkt); 304 } else if (pkt->isWrite()) { 305 accessSucceeded = ruby_system->functionalWrite(pkt); 306 } else { 307 panic("Unsupported functional command %s\n", pkt->cmdString()); 308 } 309 310 // Unless the requester explicitly said otherwise, generate an error if 311 // the functional request failed 312 if (!accessSucceeded && !pkt->suppressFuncError()) { 313 fatal("Ruby functional %s failed for address %#x\n", 314 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 315 } 316 317 if (access_phys_mem) { 318 // The attached physmem contains the official version of data. 319 // The following command performs the real functional access. 320 // This line should be removed once Ruby supplies the official version 321 // of data. 322 ruby_port->system->getPhysMem().functionalAccess(pkt); 323 } 324 325 // turn packet around to go back to requester if response expected 326 if (needsResponse) { 327 pkt->setFunctionalResponseStatus(accessSucceeded); 328 329 // @todo There should not be a reverse call since the response is 330 // communicated through the packet pointer 331 // DPRINTF(RubyPort, "Sending packet back over port\n"); 332 // sendFunctional(pkt); 333 } 334 DPRINTF(RubyPort, "Functional access %s!\n", 335 accessSucceeded ? "successful":"failed"); 336} 337 338void 339RubyPort::ruby_hit_callback(PacketPtr pkt) 340{ 341 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 342 pkt->getAddr()); 343 344 // The packet was destined for memory and has not yet been turned 345 // into a response 346 assert(system->isMemAddr(pkt->getAddr())); 347 assert(pkt->isRequest()); 348 349 // As it has not yet been turned around, the source field tells us 350 // which port it came from. 351 assert(pkt->getSrc() < slave_ports.size()); 352 353 slave_ports[pkt->getSrc()]->hitCallback(pkt); 354 355 // 356 // If we had to stall the MemSlavePorts, wake them up because the sequencer 357 // likely has free resources now. 358 // 359 if (!retryList.empty()) { 360 // 361 // Record the current list of ports to retry on a temporary list before 362 // calling sendRetry on those ports. sendRetry will cause an 363 // immediate retry, which may result in the ports being put back on the 364 // list. Therefore we want to clear the retryList before calling 365 // sendRetry. 366 // 367 std::vector<MemSlavePort *> curRetryList(retryList); 368 369 retryList.clear(); 370 371 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 372 DPRINTF(RubyPort, 373 "Sequencer may now be free. SendRetry to port %s\n", 374 (*i)->name()); 375 (*i)->sendRetry(); 376 } 377 } 378 379 testDrainComplete(); 380} 381 382void 383RubyPort::testDrainComplete() 384{ 385 //If we weren't able to drain before, we might be able to now. 386 if (drainManager != NULL) { 387 unsigned int drainCount = outstandingCount(); 388 DPRINTF(Drain, "Drain count: %u\n", drainCount); 389 if (drainCount == 0) { 390 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 391 drainManager->signalDrainDone(); 392 // Clear the drain manager once we're done with it. 393 drainManager = NULL; 394 } 395 } 396} 397 398unsigned int 399RubyPort::getChildDrainCount(DrainManager *dm) 400{ 401 int count = 0; 402 403 if (memMasterPort.isConnected()) { 404 count += memMasterPort.drain(dm); 405 DPRINTF(Config, "count after pio check %d\n", count); 406 } 407 408 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 409 count += (*p)->drain(dm); 410 DPRINTF(Config, "count after slave port check %d\n", count); 411 } 412 413 for (std::vector<PioMasterPort *>::iterator p = master_ports.begin(); 414 p != master_ports.end(); ++p) { 415 count += (*p)->drain(dm); 416 DPRINTF(Config, "count after master port check %d\n", count); 417 } 418 419 DPRINTF(Config, "final count %d\n", count); 420 return count; 421} 422 423unsigned int 424RubyPort::drain(DrainManager *dm) 425{ 426 if (isDeadlockEventScheduled()) { 427 descheduleDeadlockEvent(); 428 } 429 430 // 431 // If the RubyPort is not empty, then it needs to clear all outstanding 432 // requests before it should call drainManager->signalDrainDone() 433 // 434 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 435 bool need_drain = outstandingCount() > 0; 436 437 // 438 // Also, get the number of child ports that will also need to clear 439 // their buffered requests before they call drainManager->signalDrainDone() 440 // 441 unsigned int child_drain_count = getChildDrainCount(dm); 442 443 // Set status 444 if (need_drain) { 445 drainManager = dm; 446 447 DPRINTF(Drain, "RubyPort not drained\n"); 448 setDrainState(Drainable::Draining); 449 return child_drain_count + 1; 450 } 451 452 drainManager = NULL; 453 setDrainState(Drainable::Drained); 454 return child_drain_count; 455} 456 457void 458RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 459{ 460 bool needsResponse = pkt->needsResponse(); 461 462 // 463 // Unless specified at configuraiton, all responses except failed SC 464 // and Flush operations access M5 physical memory. 465 // 466 bool accessPhysMem = access_phys_mem; 467 468 if (pkt->isLLSC()) { 469 if (pkt->isWrite()) { 470 if (pkt->req->getExtraData() != 0) { 471 // 472 // Successful SC packets convert to normal writes 473 // 474 pkt->convertScToWrite(); 475 } else { 476 // 477 // Failed SC packets don't access physical memory and thus 478 // the RubyPort itself must convert it to a response. 479 // 480 accessPhysMem = false; 481 } 482 } else { 483 // 484 // All LL packets convert to normal loads so that M5 PhysMem does 485 // not lock the blocks. 486 // 487 pkt->convertLlToRead(); 488 } 489 } 490 491 // 492 // Flush requests don't access physical memory 493 // 494 if (pkt->isFlush()) { 495 accessPhysMem = false; 496 } 497 498 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 499 500 if (accessPhysMem) { 501 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 502 ruby_port->system->getPhysMem().access(pkt); 503 } else if (needsResponse) { 504 pkt->makeResponse(); 505 } 506 507 // turn packet around to go back to requester if response expected 508 if (needsResponse) { 509 DPRINTF(RubyPort, "Sending packet back over port\n"); 510 // send next cycle 511 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 512 } else { 513 delete pkt; 514 } 515 DPRINTF(RubyPort, "Hit callback done!\n"); 516} 517 518AddrRangeList 519RubyPort::PioSlavePort::getAddrRanges() const 520{ 521 // at the moment the assumption is that the master does not care 522 AddrRangeList ranges; 523 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 524 525 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 526 ranges.splice(ranges.begin(), 527 ruby_port->master_ports[i]->getAddrRanges()); 528 } 529 for (AddrRangeConstIter r = ranges.begin(); r != ranges.end(); ++r) 530 DPRINTF(RubyPort, "%s\n", r->to_string()); 531 return ranges; 532} 533 534bool 535RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 536{ 537 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 538 return ruby_port->system->isMemAddr(addr); 539} 540 541void 542RubyPort::ruby_eviction_callback(const Address& address) 543{ 544 DPRINTF(RubyPort, "Sending invalidations.\n"); 545 // This request is deleted in the stack-allocated packet destructor 546 // when this function exits 547 // TODO: should this really be using funcMasterId? 548 RequestPtr req = 549 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 550 // Use a single packet to signal all snooping ports of the invalidation. 551 // This assumes that snooping ports do NOT modify the packet/request 552 Packet pkt(req, MemCmd::InvalidationReq); 553 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 554 // check if the connected master port is snooping 555 if ((*p)->isSnooping()) { 556 // send as a snoop request 557 (*p)->sendTimingSnoopReq(&pkt); 558 } 559 } 560} 561 562void 563RubyPort::PioMasterPort::recvRangeChange() 564{ 565 RubyPort &r = static_cast<RubyPort &>(owner); 566 r.gotAddrRanges--; 567 if (r.gotAddrRanges == 0 && FullSystem) { 568 r.pioSlavePort.sendRangeChange(); 569 } 570} 571