RubyPort.cc revision 9270
16876Ssteve.reinhardt@amd.com/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 498923Sandreas.hansson@arm.com#include "sim/system.hh" 506285Snate@binkert.org 516876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 528922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 538922Swilliam.wang@arm.com m_mandatory_q_ptr(NULL), 548922Swilliam.wang@arm.com pio_port(csprintf("%s-pio-port", name()), this), 558922Swilliam.wang@arm.com m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 568923Sandreas.hansson@arm.com drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), 578922Swilliam.wang@arm.com waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 586876Ssteve.reinhardt@amd.com{ 596876Ssteve.reinhardt@amd.com assert(m_version != -1); 606876Ssteve.reinhardt@amd.com 618922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 628922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 638922Swilliam.wang@arm.com slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 648922Swilliam.wang@arm.com this, ruby_system, access_phys_mem)); 658922Swilliam.wang@arm.com } 667039Snate@binkert.org 678922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 688922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 698922Swilliam.wang@arm.com master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 708922Swilliam.wang@arm.com this)); 718922Swilliam.wang@arm.com } 726876Ssteve.reinhardt@amd.com} 736876Ssteve.reinhardt@amd.com 747039Snate@binkert.orgvoid 757039Snate@binkert.orgRubyPort::init() 766882SBrad.Beckmann@amd.com{ 776882SBrad.Beckmann@amd.com assert(m_controller != NULL); 786882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 796882SBrad.Beckmann@amd.com} 806882SBrad.Beckmann@amd.com 818922Swilliam.wang@arm.comMasterPort & 828922Swilliam.wang@arm.comRubyPort::getMasterPort(const std::string &if_name, int idx) 836876Ssteve.reinhardt@amd.com{ 848922Swilliam.wang@arm.com if (if_name == "pio_port") { 858922Swilliam.wang@arm.com return pio_port; 868922Swilliam.wang@arm.com } 878922Swilliam.wang@arm.com 888839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 898839Sandreas.hansson@arm.com // port 908922Swilliam.wang@arm.com if (if_name != "master") { 918922Swilliam.wang@arm.com // pass it along to our super class 928922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 938922Swilliam.wang@arm.com } else { 948922Swilliam.wang@arm.com if (idx >= static_cast<int>(master_ports.size())) { 958922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 968922Swilliam.wang@arm.com } 978839Sandreas.hansson@arm.com 988922Swilliam.wang@arm.com return *master_ports[idx]; 998839Sandreas.hansson@arm.com } 1008922Swilliam.wang@arm.com} 1018839Sandreas.hansson@arm.com 1028922Swilliam.wang@arm.comSlavePort & 1038922Swilliam.wang@arm.comRubyPort::getSlavePort(const std::string &if_name, int idx) 1048922Swilliam.wang@arm.com{ 1058922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1068922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1078922Swilliam.wang@arm.com if (if_name != "slave") { 1088922Swilliam.wang@arm.com // pass it along to our super class 1098922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1108922Swilliam.wang@arm.com } else { 1118922Swilliam.wang@arm.com if (idx >= static_cast<int>(slave_ports.size())) { 1128922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1138922Swilliam.wang@arm.com } 1148922Swilliam.wang@arm.com 1158922Swilliam.wang@arm.com return *slave_ports[idx]; 1167039Snate@binkert.org } 1176876Ssteve.reinhardt@amd.com} 1186882SBrad.Beckmann@amd.com 1197039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1206882SBrad.Beckmann@amd.com RubyPort *_port) 1218922Swilliam.wang@arm.com : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 1228922Swilliam.wang@arm.com ruby_port(_port) 1236882SBrad.Beckmann@amd.com{ 1248922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 1256882SBrad.Beckmann@amd.com} 1266882SBrad.Beckmann@amd.com 1278436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1288436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1298922Swilliam.wang@arm.com : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 1308914Sandreas.hansson@arm.com ruby_port(_port), ruby_system(_system), 1318914Sandreas.hansson@arm.com _onRetryList(false), access_phys_mem(_access_phys_mem) 1326882SBrad.Beckmann@amd.com{ 1338922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 1346882SBrad.Beckmann@amd.com} 1356882SBrad.Beckmann@amd.com 1366882SBrad.Beckmann@amd.comTick 1376882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1386882SBrad.Beckmann@amd.com{ 1396882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1406882SBrad.Beckmann@amd.com return 0; 1416882SBrad.Beckmann@amd.com} 1426882SBrad.Beckmann@amd.com 1436882SBrad.Beckmann@amd.com 1446882SBrad.Beckmann@amd.combool 1458975Sandreas.hansson@arm.comRubyPort::PioPort::recvTimingResp(PacketPtr pkt) 1466882SBrad.Beckmann@amd.com{ 1477039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1487039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1498161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1506882SBrad.Beckmann@amd.com 1516882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1527039Snate@binkert.org RubyPort::SenderState *senderState = 1536882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1546882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1556882SBrad.Beckmann@amd.com assert(port != NULL); 1567039Snate@binkert.org 1576882SBrad.Beckmann@amd.com // pop the sender state from the packet 1586882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1596882SBrad.Beckmann@amd.com delete senderState; 1607039Snate@binkert.org 1618975Sandreas.hansson@arm.com port->sendTimingResp(pkt); 1627039Snate@binkert.org 1636882SBrad.Beckmann@amd.com return true; 1646882SBrad.Beckmann@amd.com} 1656882SBrad.Beckmann@amd.com 1666882SBrad.Beckmann@amd.combool 1678975Sandreas.hansson@arm.comRubyPort::M5Port::recvTimingReq(PacketPtr pkt) 1686882SBrad.Beckmann@amd.com{ 1698161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1707039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1716882SBrad.Beckmann@amd.com 1728975Sandreas.hansson@arm.com //dsm: based on SimpleTimingPort::recvTimingReq(pkt); 1736882SBrad.Beckmann@amd.com 1747039Snate@binkert.org // The received packets should only be M5 requests, which should never 1757039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1767039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1776882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1786882SBrad.Beckmann@amd.com 1796882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1806882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1816882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1826882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1836882SBrad.Beckmann@amd.com delete pkt; 1846882SBrad.Beckmann@amd.com return true; 1856882SBrad.Beckmann@amd.com } 1866882SBrad.Beckmann@amd.com 1876922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1886922SBrad.Beckmann@amd.com // route the response 1896922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1906922SBrad.Beckmann@amd.com 1916882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1926882SBrad.Beckmann@amd.com // pio port. 1936882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1948851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 1958161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1966922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1976922SBrad.Beckmann@amd.com pkt->getAddr()); 1986882SBrad.Beckmann@amd.com 1999163Sandreas.hansson@arm.com // send next cycle 2009206Snilay@cs.wisc.edu ruby_port->pio_port.schedTimingReq(pkt, 2019206Snilay@cs.wisc.edu curTick() + g_system_ptr->clockPeriod()); 2029163Sandreas.hansson@arm.com return true; 2036882SBrad.Beckmann@amd.com } 2046882SBrad.Beckmann@amd.com 2058615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 2068615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2077906SBrad.Beckmann@amd.com 2086882SBrad.Beckmann@amd.com // Submit the ruby request 2098615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2107023SBrad.Beckmann@amd.com 2117550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2127023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2137023SBrad.Beckmann@amd.com // false. 2147550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2158161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2166922SBrad.Beckmann@amd.com return true; 2176882SBrad.Beckmann@amd.com } 2187023SBrad.Beckmann@amd.com 2197910SBrad.Beckmann@amd.com // 2207910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2217910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2227910SBrad.Beckmann@amd.com // 2237910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2247910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2257910SBrad.Beckmann@amd.com } 2267910SBrad.Beckmann@amd.com 2278161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2287906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2297039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2307039Snate@binkert.org 2316922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2326922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2336922SBrad.Beckmann@amd.com delete senderState; 2346922SBrad.Beckmann@amd.com return false; 2356882SBrad.Beckmann@amd.com} 2366882SBrad.Beckmann@amd.com 2378436SBrad.Beckmann@amd.comvoid 2388436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 2398436SBrad.Beckmann@amd.com{ 2408436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 2418436SBrad.Beckmann@amd.com pkt->getAddr()); 2428436SBrad.Beckmann@amd.com 2438436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2448436SBrad.Beckmann@amd.com // pio port. 2458436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 2468851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 2478436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 2488436SBrad.Beckmann@amd.com pkt->getAddr()); 2498436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 2508436SBrad.Beckmann@amd.com } 2518436SBrad.Beckmann@amd.com 2528436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 2538436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 2548436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2558436SBrad.Beckmann@amd.com 2568436SBrad.Beckmann@amd.com bool accessSucceeded = false; 2578436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 2588436SBrad.Beckmann@amd.com 2598436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 2608436SBrad.Beckmann@amd.com if (pkt->isRead()) { 2619270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalRead(pkt); 2628436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2639270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalWrite(pkt); 2648436SBrad.Beckmann@amd.com } else { 2658436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 2668436SBrad.Beckmann@amd.com pkt->cmdString()); 2678436SBrad.Beckmann@amd.com } 2688436SBrad.Beckmann@amd.com 2698436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 2708436SBrad.Beckmann@amd.com // the functional request failed 2718436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 2728436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 2738436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 2748436SBrad.Beckmann@amd.com } 2758436SBrad.Beckmann@amd.com 2768436SBrad.Beckmann@amd.com if (access_phys_mem) { 2778436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 2788436SBrad.Beckmann@amd.com // The following command performs the real functional access. 2798436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 2808436SBrad.Beckmann@amd.com // of data. 2818931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().functionalAccess(pkt); 2828436SBrad.Beckmann@amd.com } 2838436SBrad.Beckmann@amd.com 2848436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 2858436SBrad.Beckmann@amd.com if (needsResponse) { 2868436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 2878706Sandreas.hansson@arm.com 2888706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 2898706Sandreas.hansson@arm.com // communicated through the packet pointer 2908706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 2918706Sandreas.hansson@arm.com // sendFunctional(pkt); 2928436SBrad.Beckmann@amd.com } 2938436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 2948436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 2958436SBrad.Beckmann@amd.com} 2968436SBrad.Beckmann@amd.com 2976882SBrad.Beckmann@amd.comvoid 2986922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 2996882SBrad.Beckmann@amd.com{ 3006922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 3017039Snate@binkert.org RubyPort::SenderState *senderState = 3026922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 3036922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 3046922SBrad.Beckmann@amd.com assert(port != NULL); 3057039Snate@binkert.org 3066922SBrad.Beckmann@amd.com // pop the sender state from the packet 3076922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 3086922SBrad.Beckmann@amd.com delete senderState; 3096882SBrad.Beckmann@amd.com 3106882SBrad.Beckmann@amd.com port->hitCallback(pkt); 3117910SBrad.Beckmann@amd.com 3127910SBrad.Beckmann@amd.com // 3137910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 3147910SBrad.Beckmann@amd.com // likely has free resources now. 3157910SBrad.Beckmann@amd.com // 3167910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 3178162SBrad.Beckmann@amd.com // 3188162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3198162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3208162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3218162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3228162SBrad.Beckmann@amd.com // sendRetry. 3238162SBrad.Beckmann@amd.com // 3248162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 3258162SBrad.Beckmann@amd.com 3268162SBrad.Beckmann@amd.com retryList.clear(); 3278162SBrad.Beckmann@amd.com waitingOnSequencer = false; 3288162SBrad.Beckmann@amd.com 3298162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 3308162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 3318162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3327910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3337910SBrad.Beckmann@amd.com (*i)->name()); 3348162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 3358162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3367910SBrad.Beckmann@amd.com } 3377910SBrad.Beckmann@amd.com } 3388688Snilay@cs.wisc.edu 3398688Snilay@cs.wisc.edu testDrainComplete(); 3408688Snilay@cs.wisc.edu} 3418688Snilay@cs.wisc.edu 3428688Snilay@cs.wisc.eduvoid 3438688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 3448688Snilay@cs.wisc.edu{ 3458688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 3468688Snilay@cs.wisc.edu if (drainEvent != NULL) { 3479245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 3489152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 3498688Snilay@cs.wisc.edu if (drainCount == 0) { 3509152Satgutier@umich.edu DPRINTF(Drain, "RubyPort done draining, processing drain event\n"); 3518688Snilay@cs.wisc.edu drainEvent->process(); 3528688Snilay@cs.wisc.edu // Clear the drain event once we're done with it. 3538688Snilay@cs.wisc.edu drainEvent = NULL; 3548688Snilay@cs.wisc.edu } 3558688Snilay@cs.wisc.edu } 3568688Snilay@cs.wisc.edu} 3578688Snilay@cs.wisc.edu 3588688Snilay@cs.wisc.eduunsigned int 3599245Shestness@cs.wisc.eduRubyPort::getChildDrainCount(Event *de) 3608688Snilay@cs.wisc.edu{ 3618688Snilay@cs.wisc.edu int count = 0; 3628688Snilay@cs.wisc.edu 3638851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 3648851Sandreas.hansson@arm.com count += pio_port.drain(de); 3658688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 3668688Snilay@cs.wisc.edu } 3678688Snilay@cs.wisc.edu 3688922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 3698922Swilliam.wang@arm.com count += (*p)->drain(de); 3708922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 3718922Swilliam.wang@arm.com } 3728922Swilliam.wang@arm.com 3738922Swilliam.wang@arm.com for (std::vector<PioPort*>::iterator p = master_ports.begin(); 3748922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 3758922Swilliam.wang@arm.com count += (*p)->drain(de); 3768922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 3778688Snilay@cs.wisc.edu } 3788688Snilay@cs.wisc.edu 3798688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 3808688Snilay@cs.wisc.edu 3818688Snilay@cs.wisc.edu return count; 3828688Snilay@cs.wisc.edu} 3838688Snilay@cs.wisc.edu 3848688Snilay@cs.wisc.eduunsigned int 3858688Snilay@cs.wisc.eduRubyPort::drain(Event *de) 3868688Snilay@cs.wisc.edu{ 3878688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 3888688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 3898688Snilay@cs.wisc.edu } 3908688Snilay@cs.wisc.edu 3919245Shestness@cs.wisc.edu // 3929245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 3939245Shestness@cs.wisc.edu // requests before it should call drainEvent->process() 3949245Shestness@cs.wisc.edu // 3959245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 3969245Shestness@cs.wisc.edu bool need_drain = outstandingCount() > 0; 3979245Shestness@cs.wisc.edu 3989245Shestness@cs.wisc.edu // 3999245Shestness@cs.wisc.edu // Also, get the number of child ports that will also need to clear 4009245Shestness@cs.wisc.edu // their buffered requests before they call drainEvent->process() 4019245Shestness@cs.wisc.edu // 4029245Shestness@cs.wisc.edu unsigned int child_drain_count = getChildDrainCount(de); 4038688Snilay@cs.wisc.edu 4048688Snilay@cs.wisc.edu // Set status 4059245Shestness@cs.wisc.edu if (need_drain) { 4068688Snilay@cs.wisc.edu drainEvent = de; 4078688Snilay@cs.wisc.edu 4089152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 4098688Snilay@cs.wisc.edu changeState(SimObject::Draining); 4109245Shestness@cs.wisc.edu return child_drain_count + 1; 4118688Snilay@cs.wisc.edu } 4128688Snilay@cs.wisc.edu 4139245Shestness@cs.wisc.edu drainEvent = NULL; 4148688Snilay@cs.wisc.edu changeState(SimObject::Drained); 4159245Shestness@cs.wisc.edu return child_drain_count; 4166882SBrad.Beckmann@amd.com} 4176882SBrad.Beckmann@amd.com 4186882SBrad.Beckmann@amd.comvoid 4196882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 4206882SBrad.Beckmann@amd.com{ 4216882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4226882SBrad.Beckmann@amd.com 4237550SBrad.Beckmann@amd.com // 4247915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 4258184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 4267550SBrad.Beckmann@amd.com // 4277915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 4287550SBrad.Beckmann@amd.com 4297550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4307550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4317550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4327550SBrad.Beckmann@amd.com // 4337550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4347550SBrad.Beckmann@amd.com // 4357550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4367550SBrad.Beckmann@amd.com } else { 4377550SBrad.Beckmann@amd.com // 4387550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4397550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4407550SBrad.Beckmann@amd.com // 4417550SBrad.Beckmann@amd.com accessPhysMem = false; 4427550SBrad.Beckmann@amd.com } 4437550SBrad.Beckmann@amd.com } else { 4447550SBrad.Beckmann@amd.com // 4457550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4467550SBrad.Beckmann@amd.com // not lock the blocks. 4477550SBrad.Beckmann@amd.com // 4487550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4497550SBrad.Beckmann@amd.com } 4507550SBrad.Beckmann@amd.com } 4518184Ssomayeh@cs.wisc.edu 4528184Ssomayeh@cs.wisc.edu // 4538184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4548184Ssomayeh@cs.wisc.edu // 4558184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4568184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4578184Ssomayeh@cs.wisc.edu } 4588184Ssomayeh@cs.wisc.edu 4598161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4606882SBrad.Beckmann@amd.com 4617550SBrad.Beckmann@amd.com if (accessPhysMem) { 4628931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().access(pkt); 4638184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4647915SBrad.Beckmann@amd.com pkt->makeResponse(); 4657550SBrad.Beckmann@amd.com } 4666882SBrad.Beckmann@amd.com 4676882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4686882SBrad.Beckmann@amd.com if (needsResponse) { 4698161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4709163Sandreas.hansson@arm.com // send next cycle 4719206Snilay@cs.wisc.edu schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 4726882SBrad.Beckmann@amd.com } else { 4736882SBrad.Beckmann@amd.com delete pkt; 4746882SBrad.Beckmann@amd.com } 4758161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 4766882SBrad.Beckmann@amd.com} 4776882SBrad.Beckmann@amd.com 4788922Swilliam.wang@arm.comAddrRangeList 4799090Sandreas.hansson@arm.comRubyPort::M5Port::getAddrRanges() const 4808922Swilliam.wang@arm.com{ 4818922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 4828922Swilliam.wang@arm.com AddrRangeList ranges; 4838922Swilliam.wang@arm.com return ranges; 4848922Swilliam.wang@arm.com} 4858922Swilliam.wang@arm.com 4866882SBrad.Beckmann@amd.combool 4876882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 4886882SBrad.Beckmann@amd.com{ 4898931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 4906882SBrad.Beckmann@amd.com} 4917909Shestness@cs.utexas.edu 4927909Shestness@cs.utexas.eduunsigned 4937909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 4947909Shestness@cs.utexas.edu{ 4957909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 4967909Shestness@cs.utexas.edu} 4978717Snilay@cs.wisc.edu 4988717Snilay@cs.wisc.eduvoid 4998717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 5008717Snilay@cs.wisc.edu{ 5018717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 5028922Swilliam.wang@arm.com // should this really be using funcMasterId? 5038832SAli.Saidi@ARM.com Request req(address.getAddress(), 0, 0, Request::funcMasterId); 5048922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 5059088Sandreas.hansson@arm.com // check if the connected master port is snooping 5069088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 5078949Sandreas.hansson@arm.com Packet *pkt = new Packet(&req, MemCmd::InvalidationReq); 5088948Sandreas.hansson@arm.com // send as a snoop request 5098978Sandreas.hansson@arm.com (*p)->sendTimingSnoopReq(pkt); 5108922Swilliam.wang@arm.com } 5118717Snilay@cs.wisc.edu } 5128717Snilay@cs.wisc.edu} 513