RubyPort.cc revision 8174
16876Ssteve.reinhardt@amd.com/* 26876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 36876Ssteve.reinhardt@amd.com * All rights reserved. 46876Ssteve.reinhardt@amd.com * 56876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 66876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 76876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 86876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 96876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 106876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 126876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 136876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 146876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 156876Ssteve.reinhardt@amd.com * 166876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276876Ssteve.reinhardt@amd.com */ 286876Ssteve.reinhardt@amd.com 297908Shestness@cs.utexas.edu#include "config/the_isa.hh" 307908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 317908Shestness@cs.utexas.edu#include "arch/x86/insts/microldstop.hh" 327908Shestness@cs.utexas.edu#endif // X86_ISA 337632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 346876Ssteve.reinhardt@amd.com#include "mem/physical.hh" 357039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 366285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 376285Snate@binkert.org 386876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 396893SBrad.Beckmann@amd.com : MemObject(p) 406876Ssteve.reinhardt@amd.com{ 416876Ssteve.reinhardt@amd.com m_version = p->version; 426876Ssteve.reinhardt@amd.com assert(m_version != -1); 436876Ssteve.reinhardt@amd.com 446893SBrad.Beckmann@amd.com physmem = p->physmem; 457039Snate@binkert.org 466882SBrad.Beckmann@amd.com m_controller = NULL; 476882SBrad.Beckmann@amd.com m_mandatory_q_ptr = NULL; 486876Ssteve.reinhardt@amd.com 496876Ssteve.reinhardt@amd.com m_request_cnt = 0; 506882SBrad.Beckmann@amd.com pio_port = NULL; 516893SBrad.Beckmann@amd.com physMemPort = NULL; 527910SBrad.Beckmann@amd.com 537910SBrad.Beckmann@amd.com m_usingRubyTester = p->using_ruby_tester; 547915SBrad.Beckmann@amd.com access_phys_mem = p->access_phys_mem; 556876Ssteve.reinhardt@amd.com} 566876Ssteve.reinhardt@amd.com 577039Snate@binkert.orgvoid 587039Snate@binkert.orgRubyPort::init() 596882SBrad.Beckmann@amd.com{ 606882SBrad.Beckmann@amd.com assert(m_controller != NULL); 616882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 626882SBrad.Beckmann@amd.com} 636882SBrad.Beckmann@amd.com 646876Ssteve.reinhardt@amd.comPort * 656876Ssteve.reinhardt@amd.comRubyPort::getPort(const std::string &if_name, int idx) 666876Ssteve.reinhardt@amd.com{ 676882SBrad.Beckmann@amd.com if (if_name == "port") { 687915SBrad.Beckmann@amd.com return new M5Port(csprintf("%s-port%d", name(), idx), this, 697915SBrad.Beckmann@amd.com access_phys_mem); 707039Snate@binkert.org } 717039Snate@binkert.org 727039Snate@binkert.org if (if_name == "pio_port") { 736882SBrad.Beckmann@amd.com // ensure there is only one pio port 746882SBrad.Beckmann@amd.com assert(pio_port == NULL); 756882SBrad.Beckmann@amd.com 767039Snate@binkert.org pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this); 776882SBrad.Beckmann@amd.com 786882SBrad.Beckmann@amd.com return pio_port; 797039Snate@binkert.org } 807039Snate@binkert.org 817039Snate@binkert.org if (if_name == "physMemPort") { 826893SBrad.Beckmann@amd.com // RubyPort should only have one port to physical memory 836893SBrad.Beckmann@amd.com assert (physMemPort == NULL); 846893SBrad.Beckmann@amd.com 857915SBrad.Beckmann@amd.com physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, 867915SBrad.Beckmann@amd.com access_phys_mem); 877039Snate@binkert.org 886893SBrad.Beckmann@amd.com return physMemPort; 897039Snate@binkert.org } 907039Snate@binkert.org 917039Snate@binkert.org if (if_name == "functional") { 927039Snate@binkert.org // Calls for the functional port only want to access 937039Snate@binkert.org // functional memory. Therefore, directly pass these calls 947039Snate@binkert.org // ports to physmem. 956893SBrad.Beckmann@amd.com assert(physmem != NULL); 966893SBrad.Beckmann@amd.com return physmem->getPort(if_name, idx); 976882SBrad.Beckmann@amd.com } 987039Snate@binkert.org 996876Ssteve.reinhardt@amd.com return NULL; 1006876Ssteve.reinhardt@amd.com} 1016882SBrad.Beckmann@amd.com 1027039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1036882SBrad.Beckmann@amd.com RubyPort *_port) 1046882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1056882SBrad.Beckmann@amd.com{ 1068161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name); 1076882SBrad.Beckmann@amd.com ruby_port = _port; 1086882SBrad.Beckmann@amd.com} 1096882SBrad.Beckmann@amd.com 1107039Snate@binkert.orgRubyPort::M5Port::M5Port(const std::string &_name, 1117915SBrad.Beckmann@amd.com RubyPort *_port, bool _access_phys_mem) 1126882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1136882SBrad.Beckmann@amd.com{ 1148161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name); 1156882SBrad.Beckmann@amd.com ruby_port = _port; 1167910SBrad.Beckmann@amd.com _onRetryList = false; 1177915SBrad.Beckmann@amd.com access_phys_mem = _access_phys_mem; 1186882SBrad.Beckmann@amd.com} 1196882SBrad.Beckmann@amd.com 1206882SBrad.Beckmann@amd.comTick 1216882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1226882SBrad.Beckmann@amd.com{ 1236882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1246882SBrad.Beckmann@amd.com return 0; 1256882SBrad.Beckmann@amd.com} 1266882SBrad.Beckmann@amd.com 1276882SBrad.Beckmann@amd.comTick 1286882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1296882SBrad.Beckmann@amd.com{ 1306882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1316882SBrad.Beckmann@amd.com return 0; 1326882SBrad.Beckmann@amd.com} 1336882SBrad.Beckmann@amd.com 1346882SBrad.Beckmann@amd.com 1356882SBrad.Beckmann@amd.combool 1366882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1376882SBrad.Beckmann@amd.com{ 1387039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1397039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1408161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1416882SBrad.Beckmann@amd.com 1426882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1436882SBrad.Beckmann@amd.com 1446882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1457039Snate@binkert.org RubyPort::SenderState *senderState = 1466882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1476882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1486882SBrad.Beckmann@amd.com assert(port != NULL); 1497039Snate@binkert.org 1506882SBrad.Beckmann@amd.com // pop the sender state from the packet 1516882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1526882SBrad.Beckmann@amd.com delete senderState; 1537039Snate@binkert.org 1546882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1557039Snate@binkert.org 1566882SBrad.Beckmann@amd.com return true; 1576882SBrad.Beckmann@amd.com} 1586882SBrad.Beckmann@amd.com 1596882SBrad.Beckmann@amd.combool 1606882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1616882SBrad.Beckmann@amd.com{ 1628161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1637039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1646882SBrad.Beckmann@amd.com 1656882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1666882SBrad.Beckmann@amd.com 1677039Snate@binkert.org // The received packets should only be M5 requests, which should never 1687039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1697039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1706882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1716882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1726882SBrad.Beckmann@amd.com 1736882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1746882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1756882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1766882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1776882SBrad.Beckmann@amd.com delete pkt; 1786882SBrad.Beckmann@amd.com return true; 1796882SBrad.Beckmann@amd.com } 1806882SBrad.Beckmann@amd.com 1816922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1826922SBrad.Beckmann@amd.com // route the response 1836922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1846922SBrad.Beckmann@amd.com 1856882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1866882SBrad.Beckmann@amd.com // pio port. 1876882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1886882SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 1898161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1906922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1916922SBrad.Beckmann@amd.com pkt->getAddr()); 1926882SBrad.Beckmann@amd.com 1936882SBrad.Beckmann@amd.com return ruby_port->pio_port->sendTiming(pkt); 1946882SBrad.Beckmann@amd.com } 1956882SBrad.Beckmann@amd.com 1966882SBrad.Beckmann@amd.com // For DMA and CPU requests, translate them to ruby requests before 1976882SBrad.Beckmann@amd.com // sending them to our assigned ruby port. 1986882SBrad.Beckmann@amd.com RubyRequestType type = RubyRequestType_NULL; 1996899SBrad.Beckmann@amd.com 2006899SBrad.Beckmann@amd.com // If valid, copy the pc to the ruby request 2016882SBrad.Beckmann@amd.com Addr pc = 0; 2026899SBrad.Beckmann@amd.com if (pkt->req->hasPC()) { 2036899SBrad.Beckmann@amd.com pc = pkt->req->getPC(); 2046899SBrad.Beckmann@amd.com } 2056899SBrad.Beckmann@amd.com 2067023SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 2077023SBrad.Beckmann@amd.com if (pkt->isWrite()) { 2088161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing SC\n"); 2097907Shestness@cs.utexas.edu type = RubyRequestType_Store_Conditional; 2106882SBrad.Beckmann@amd.com } else { 2118161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing LL\n"); 2127023SBrad.Beckmann@amd.com assert(pkt->isRead()); 2137907Shestness@cs.utexas.edu type = RubyRequestType_Load_Linked; 2146882SBrad.Beckmann@amd.com } 2157908Shestness@cs.utexas.edu } else if (pkt->req->isLocked()) { 2167908Shestness@cs.utexas.edu if (pkt->isWrite()) { 2178161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Write\n"); 2187908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Write; 2197908Shestness@cs.utexas.edu } else { 2208161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Read\n"); 2217908Shestness@cs.utexas.edu assert(pkt->isRead()); 2227908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Read; 2237908Shestness@cs.utexas.edu } 2246922SBrad.Beckmann@amd.com } else { 2257023SBrad.Beckmann@amd.com if (pkt->isRead()) { 2267023SBrad.Beckmann@amd.com if (pkt->req->isInstFetch()) { 2277023SBrad.Beckmann@amd.com type = RubyRequestType_IFETCH; 2287023SBrad.Beckmann@amd.com } else { 2297908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 2307908Shestness@cs.utexas.edu uint32_t flags = pkt->req->getFlags(); 2317908Shestness@cs.utexas.edu bool storeCheck = flags & 2327908Shestness@cs.utexas.edu (TheISA::StoreCheck << TheISA::FlagShift); 2337908Shestness@cs.utexas.edu#else 2347908Shestness@cs.utexas.edu bool storeCheck = false; 2357908Shestness@cs.utexas.edu#endif // X86_ISA 2367908Shestness@cs.utexas.edu if (storeCheck) { 2377908Shestness@cs.utexas.edu type = RubyRequestType_RMW_Read; 2387908Shestness@cs.utexas.edu } else { 2397908Shestness@cs.utexas.edu type = RubyRequestType_LD; 2407908Shestness@cs.utexas.edu } 2417023SBrad.Beckmann@amd.com } 2427023SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2437908Shestness@cs.utexas.edu // 2447908Shestness@cs.utexas.edu // Note: M5 packets do not differentiate ST from RMW_Write 2457908Shestness@cs.utexas.edu // 2467023SBrad.Beckmann@amd.com type = RubyRequestType_ST; 2477023SBrad.Beckmann@amd.com } else { 2487023SBrad.Beckmann@amd.com panic("Unsupported ruby packet type\n"); 2497023SBrad.Beckmann@amd.com } 2506882SBrad.Beckmann@amd.com } 2516882SBrad.Beckmann@amd.com 2527915SBrad.Beckmann@amd.com RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true), 2537039Snate@binkert.org pkt->getSize(), pc, type, 2547039Snate@binkert.org RubyAccessMode_Supervisor, pkt); 2556882SBrad.Beckmann@amd.com 2568174Snilay@cs.wisc.edu assert(ruby_request.m_PhysicalAddress.getOffset() + ruby_request.m_Size <= 2577906SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2587906SBrad.Beckmann@amd.com 2596882SBrad.Beckmann@amd.com // Submit the ruby request 2606922SBrad.Beckmann@amd.com RequestStatus requestStatus = ruby_port->makeRequest(ruby_request); 2617023SBrad.Beckmann@amd.com 2627550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2637023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2647023SBrad.Beckmann@amd.com // false. 2657550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2668161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2676922SBrad.Beckmann@amd.com return true; 2686882SBrad.Beckmann@amd.com } 2697023SBrad.Beckmann@amd.com 2707910SBrad.Beckmann@amd.com // 2717910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2727910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2737910SBrad.Beckmann@amd.com // 2747910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2757910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2767910SBrad.Beckmann@amd.com } 2777910SBrad.Beckmann@amd.com 2788161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2797906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2807039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2817039Snate@binkert.org 2826922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2836922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2846922SBrad.Beckmann@amd.com delete senderState; 2856922SBrad.Beckmann@amd.com return false; 2866882SBrad.Beckmann@amd.com} 2876882SBrad.Beckmann@amd.com 2886882SBrad.Beckmann@amd.comvoid 2896922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 2906882SBrad.Beckmann@amd.com{ 2916922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 2927039Snate@binkert.org RubyPort::SenderState *senderState = 2936922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 2946922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 2956922SBrad.Beckmann@amd.com assert(port != NULL); 2967039Snate@binkert.org 2976922SBrad.Beckmann@amd.com // pop the sender state from the packet 2986922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2996922SBrad.Beckmann@amd.com delete senderState; 3006882SBrad.Beckmann@amd.com 3016882SBrad.Beckmann@amd.com port->hitCallback(pkt); 3027910SBrad.Beckmann@amd.com 3037910SBrad.Beckmann@amd.com // 3047910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 3057910SBrad.Beckmann@amd.com // likely has free resources now. 3067910SBrad.Beckmann@amd.com // 3077910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 3088162SBrad.Beckmann@amd.com // 3098162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3108162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3118162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3128162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3138162SBrad.Beckmann@amd.com // sendRetry. 3148162SBrad.Beckmann@amd.com // 3158162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 3168162SBrad.Beckmann@amd.com 3178162SBrad.Beckmann@amd.com retryList.clear(); 3188162SBrad.Beckmann@amd.com waitingOnSequencer = false; 3198162SBrad.Beckmann@amd.com 3208162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 3218162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 3228162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3237910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3247910SBrad.Beckmann@amd.com (*i)->name()); 3258162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 3268162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3277910SBrad.Beckmann@amd.com } 3287910SBrad.Beckmann@amd.com } 3296882SBrad.Beckmann@amd.com} 3306882SBrad.Beckmann@amd.com 3316882SBrad.Beckmann@amd.comvoid 3326882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 3336882SBrad.Beckmann@amd.com{ 3346882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 3356882SBrad.Beckmann@amd.com 3367550SBrad.Beckmann@amd.com // 3377915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 3387915SBrad.Beckmann@amd.com // operations access M5 physical memory. 3397550SBrad.Beckmann@amd.com // 3407915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 3417550SBrad.Beckmann@amd.com 3427550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 3437550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 3447550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 3457550SBrad.Beckmann@amd.com // 3467550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 3477550SBrad.Beckmann@amd.com // 3487550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 3497550SBrad.Beckmann@amd.com } else { 3507550SBrad.Beckmann@amd.com // 3517550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 3527550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 3537550SBrad.Beckmann@amd.com // 3547550SBrad.Beckmann@amd.com accessPhysMem = false; 3557550SBrad.Beckmann@amd.com } 3567550SBrad.Beckmann@amd.com } else { 3577550SBrad.Beckmann@amd.com // 3587550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 3597550SBrad.Beckmann@amd.com // not lock the blocks. 3607550SBrad.Beckmann@amd.com // 3617550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 3627550SBrad.Beckmann@amd.com } 3637550SBrad.Beckmann@amd.com } 3648161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 3656882SBrad.Beckmann@amd.com 3667550SBrad.Beckmann@amd.com if (accessPhysMem) { 3677550SBrad.Beckmann@amd.com ruby_port->physMemPort->sendAtomic(pkt); 3687915SBrad.Beckmann@amd.com } else { 3697915SBrad.Beckmann@amd.com pkt->makeResponse(); 3707550SBrad.Beckmann@amd.com } 3716882SBrad.Beckmann@amd.com 3726882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 3736882SBrad.Beckmann@amd.com if (needsResponse) { 3748161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 3756882SBrad.Beckmann@amd.com sendTiming(pkt); 3766882SBrad.Beckmann@amd.com } else { 3776882SBrad.Beckmann@amd.com delete pkt; 3786882SBrad.Beckmann@amd.com } 3798161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 3806882SBrad.Beckmann@amd.com} 3816882SBrad.Beckmann@amd.com 3826882SBrad.Beckmann@amd.combool 3836882SBrad.Beckmann@amd.comRubyPort::M5Port::sendTiming(PacketPtr pkt) 3846882SBrad.Beckmann@amd.com{ 3857558SBrad.Beckmann@amd.com //minimum latency, must be > 0 3867823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 3876882SBrad.Beckmann@amd.com return true; 3886882SBrad.Beckmann@amd.com} 3896882SBrad.Beckmann@amd.com 3906882SBrad.Beckmann@amd.combool 3916882SBrad.Beckmann@amd.comRubyPort::PioPort::sendTiming(PacketPtr pkt) 3926882SBrad.Beckmann@amd.com{ 3937558SBrad.Beckmann@amd.com //minimum latency, must be > 0 3947823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 3956882SBrad.Beckmann@amd.com return true; 3966882SBrad.Beckmann@amd.com} 3976882SBrad.Beckmann@amd.com 3986882SBrad.Beckmann@amd.combool 3996882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 4006882SBrad.Beckmann@amd.com{ 4016882SBrad.Beckmann@amd.com AddrRangeList physMemAddrList; 4026882SBrad.Beckmann@amd.com bool snoop = false; 4036893SBrad.Beckmann@amd.com ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop); 4047039Snate@binkert.org for (AddrRangeIter iter = physMemAddrList.begin(); 4057039Snate@binkert.org iter != physMemAddrList.end(); 4067039Snate@binkert.org iter++) { 4076882SBrad.Beckmann@amd.com if (addr >= iter->start && addr <= iter->end) { 4088161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 4096882SBrad.Beckmann@amd.com iter->start, iter->end); 4106882SBrad.Beckmann@amd.com return true; 4116882SBrad.Beckmann@amd.com } 4126882SBrad.Beckmann@amd.com } 4136882SBrad.Beckmann@amd.com return false; 4146882SBrad.Beckmann@amd.com} 4157909Shestness@cs.utexas.edu 4167909Shestness@cs.utexas.eduunsigned 4177909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 4187909Shestness@cs.utexas.edu{ 4197909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 4207909Shestness@cs.utexas.edu} 421