GPUCoalescer.hh revision 12133
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2013-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. 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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: Sooraj Puthoor 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#ifndef __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__ 3711308Santhony.gutierrez@amd.com#define __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__ 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.com#include <iostream> 4011308Santhony.gutierrez@amd.com#include <unordered_map> 4111308Santhony.gutierrez@amd.com 4211308Santhony.gutierrez@amd.com#include "base/statistics.hh" 4311308Santhony.gutierrez@amd.com#include "mem/protocol/HSAScope.hh" 4411308Santhony.gutierrez@amd.com#include "mem/protocol/HSASegment.hh" 4511308Santhony.gutierrez@amd.com#include "mem/protocol/PrefetchBit.hh" 4611308Santhony.gutierrez@amd.com#include "mem/protocol/RubyAccessMode.hh" 4711308Santhony.gutierrez@amd.com#include "mem/protocol/RubyRequestType.hh" 4811308Santhony.gutierrez@amd.com#include "mem/protocol/SequencerRequestType.hh" 4911308Santhony.gutierrez@amd.com#include "mem/request.hh" 5011308Santhony.gutierrez@amd.com#include "mem/ruby/common/Address.hh" 5111308Santhony.gutierrez@amd.com#include "mem/ruby/common/Consumer.hh" 5211900Sandreas.sandberg@arm.com#include "mem/ruby/system/Sequencer.hh" 5311308Santhony.gutierrez@amd.com 5411308Santhony.gutierrez@amd.comclass DataBlock; 5511308Santhony.gutierrez@amd.comclass CacheMsg; 5611308Santhony.gutierrez@amd.comclass MachineID; 5711308Santhony.gutierrez@amd.comclass CacheMemory; 5811308Santhony.gutierrez@amd.com 5911308Santhony.gutierrez@amd.comclass RubyGPUCoalescerParams; 6011308Santhony.gutierrez@amd.com 6111308Santhony.gutierrez@amd.comHSAScope reqScopeToHSAScope(Request* req); 6211308Santhony.gutierrez@amd.comHSASegment reqSegmentToHSASegment(Request* req); 6311308Santhony.gutierrez@amd.com 6411308Santhony.gutierrez@amd.comstruct GPUCoalescerRequest 6511308Santhony.gutierrez@amd.com{ 6611308Santhony.gutierrez@amd.com PacketPtr pkt; 6711308Santhony.gutierrez@amd.com RubyRequestType m_type; 6811308Santhony.gutierrez@amd.com Cycles issue_time; 6911308Santhony.gutierrez@amd.com 7011308Santhony.gutierrez@amd.com GPUCoalescerRequest(PacketPtr _pkt, RubyRequestType _m_type, 7111308Santhony.gutierrez@amd.com Cycles _issue_time) 7211308Santhony.gutierrez@amd.com : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 7311308Santhony.gutierrez@amd.com {} 7411308Santhony.gutierrez@amd.com}; 7511308Santhony.gutierrez@amd.com 7611689Santhony.gutierrez@amd.comclass RequestDesc 7711689Santhony.gutierrez@amd.com{ 7811689Santhony.gutierrez@amd.com public: 7911689Santhony.gutierrez@amd.com RequestDesc(PacketPtr pkt, RubyRequestType p_type, RubyRequestType s_type) 8011689Santhony.gutierrez@amd.com : pkt(pkt), primaryType(p_type), secondaryType(s_type) 8111689Santhony.gutierrez@amd.com { 8211689Santhony.gutierrez@amd.com } 8311689Santhony.gutierrez@amd.com 8411689Santhony.gutierrez@amd.com RequestDesc() : pkt(nullptr), primaryType(RubyRequestType_NULL), 8511689Santhony.gutierrez@amd.com secondaryType(RubyRequestType_NULL) 8611689Santhony.gutierrez@amd.com { 8711689Santhony.gutierrez@amd.com } 8811689Santhony.gutierrez@amd.com 8911689Santhony.gutierrez@amd.com PacketPtr pkt; 9011689Santhony.gutierrez@amd.com RubyRequestType primaryType; 9111689Santhony.gutierrez@amd.com RubyRequestType secondaryType; 9211689Santhony.gutierrez@amd.com}; 9311689Santhony.gutierrez@amd.com 9411308Santhony.gutierrez@amd.comstd::ostream& operator<<(std::ostream& out, const GPUCoalescerRequest& obj); 9511308Santhony.gutierrez@amd.com 9611308Santhony.gutierrez@amd.comclass GPUCoalescer : public RubyPort 9711308Santhony.gutierrez@amd.com{ 9811308Santhony.gutierrez@amd.com public: 9911308Santhony.gutierrez@amd.com typedef RubyGPUCoalescerParams Params; 10011308Santhony.gutierrez@amd.com GPUCoalescer(const Params *); 10111308Santhony.gutierrez@amd.com ~GPUCoalescer(); 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com // Public Methods 10411308Santhony.gutierrez@amd.com void wakeup(); // Used only for deadlock detection 10511308Santhony.gutierrez@amd.com 10611308Santhony.gutierrez@amd.com void printProgress(std::ostream& out) const; 10711308Santhony.gutierrez@amd.com void resetStats(); 10811308Santhony.gutierrez@amd.com void collateStats(); 10911308Santhony.gutierrez@amd.com void regStats(); 11011308Santhony.gutierrez@amd.com 11111308Santhony.gutierrez@amd.com void writeCallback(Addr address, DataBlock& data); 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com void writeCallback(Addr address, 11411308Santhony.gutierrez@amd.com MachineType mach, 11511308Santhony.gutierrez@amd.com DataBlock& data); 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.com void writeCallback(Addr address, 11811308Santhony.gutierrez@amd.com MachineType mach, 11911308Santhony.gutierrez@amd.com DataBlock& data, 12011308Santhony.gutierrez@amd.com Cycles initialRequestTime, 12111308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 12211308Santhony.gutierrez@amd.com Cycles firstResponseTime, 12311308Santhony.gutierrez@amd.com bool isRegion); 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com void writeCallback(Addr address, 12611308Santhony.gutierrez@amd.com MachineType mach, 12711308Santhony.gutierrez@amd.com DataBlock& data, 12811308Santhony.gutierrez@amd.com Cycles initialRequestTime, 12911308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 13011308Santhony.gutierrez@amd.com Cycles firstResponseTime); 13111308Santhony.gutierrez@amd.com 13211308Santhony.gutierrez@amd.com void readCallback(Addr address, DataBlock& data); 13311308Santhony.gutierrez@amd.com 13411308Santhony.gutierrez@amd.com void readCallback(Addr address, 13511308Santhony.gutierrez@amd.com MachineType mach, 13611308Santhony.gutierrez@amd.com DataBlock& data); 13711308Santhony.gutierrez@amd.com 13811308Santhony.gutierrez@amd.com void readCallback(Addr address, 13911308Santhony.gutierrez@amd.com MachineType mach, 14011308Santhony.gutierrez@amd.com DataBlock& data, 14111308Santhony.gutierrez@amd.com Cycles initialRequestTime, 14211308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 14311308Santhony.gutierrez@amd.com Cycles firstResponseTime); 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com void readCallback(Addr address, 14611308Santhony.gutierrez@amd.com MachineType mach, 14711308Santhony.gutierrez@amd.com DataBlock& data, 14811308Santhony.gutierrez@amd.com Cycles initialRequestTime, 14911308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 15011308Santhony.gutierrez@amd.com Cycles firstResponseTime, 15111308Santhony.gutierrez@amd.com bool isRegion); 15211308Santhony.gutierrez@amd.com /* atomics need their own callback because the data 15311308Santhony.gutierrez@amd.com might be const coming from SLICC */ 15411308Santhony.gutierrez@amd.com void atomicCallback(Addr address, 15511308Santhony.gutierrez@amd.com MachineType mach, 15611308Santhony.gutierrez@amd.com const DataBlock& data); 15711308Santhony.gutierrez@amd.com 15811308Santhony.gutierrez@amd.com void recordCPReadCallBack(MachineID myMachID, MachineID senderMachID); 15911308Santhony.gutierrez@amd.com void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID); 16011308Santhony.gutierrez@amd.com 16111308Santhony.gutierrez@amd.com // Alternate implementations in VIPER Coalescer 16211308Santhony.gutierrez@amd.com virtual RequestStatus makeRequest(PacketPtr pkt); 16311308Santhony.gutierrez@amd.com 16411308Santhony.gutierrez@amd.com int outstandingCount() const { return m_outstanding_count; } 16511308Santhony.gutierrez@amd.com 16611308Santhony.gutierrez@amd.com bool 16711308Santhony.gutierrez@amd.com isDeadlockEventScheduled() const 16811308Santhony.gutierrez@amd.com { 16911308Santhony.gutierrez@amd.com return deadlockCheckEvent.scheduled(); 17011308Santhony.gutierrez@amd.com } 17111308Santhony.gutierrez@amd.com 17211308Santhony.gutierrez@amd.com void 17311308Santhony.gutierrez@amd.com descheduleDeadlockEvent() 17411308Santhony.gutierrez@amd.com { 17511308Santhony.gutierrez@amd.com deschedule(deadlockCheckEvent); 17611308Santhony.gutierrez@amd.com } 17711308Santhony.gutierrez@amd.com 17811308Santhony.gutierrez@amd.com bool empty() const; 17911308Santhony.gutierrez@amd.com 18011308Santhony.gutierrez@amd.com void print(std::ostream& out) const; 18111308Santhony.gutierrez@amd.com void checkCoherence(Addr address); 18211308Santhony.gutierrez@amd.com 18311308Santhony.gutierrez@amd.com void markRemoved(); 18411308Santhony.gutierrez@amd.com void removeRequest(GPUCoalescerRequest* request); 18511308Santhony.gutierrez@amd.com void evictionCallback(Addr address); 18611308Santhony.gutierrez@amd.com void completeIssue(); 18711308Santhony.gutierrez@amd.com 18811308Santhony.gutierrez@amd.com void insertKernel(int wavefront_id, PacketPtr pkt); 18911308Santhony.gutierrez@amd.com 19011308Santhony.gutierrez@amd.com void recordRequestType(SequencerRequestType requestType); 19111308Santhony.gutierrez@amd.com Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } 19211308Santhony.gutierrez@amd.com 19311308Santhony.gutierrez@amd.com Stats::Histogram& getLatencyHist() { return m_latencyHist; } 19411308Santhony.gutierrez@amd.com Stats::Histogram& getTypeLatencyHist(uint32_t t) 19511308Santhony.gutierrez@amd.com { return *m_typeLatencyHist[t]; } 19611308Santhony.gutierrez@amd.com 19711308Santhony.gutierrez@amd.com Stats::Histogram& getMissLatencyHist() 19811308Santhony.gutierrez@amd.com { return m_missLatencyHist; } 19911308Santhony.gutierrez@amd.com Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 20011308Santhony.gutierrez@amd.com { return *m_missTypeLatencyHist[t]; } 20111308Santhony.gutierrez@amd.com 20211308Santhony.gutierrez@amd.com Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 20311308Santhony.gutierrez@amd.com { return *m_missMachLatencyHist[t]; } 20411308Santhony.gutierrez@amd.com 20511308Santhony.gutierrez@amd.com Stats::Histogram& 20611308Santhony.gutierrez@amd.com getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 20711308Santhony.gutierrez@amd.com { return *m_missTypeMachLatencyHist[r][t]; } 20811308Santhony.gutierrez@amd.com 20911308Santhony.gutierrez@amd.com Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 21011308Santhony.gutierrez@amd.com { return *m_IssueToInitialDelayHist[t]; } 21111308Santhony.gutierrez@amd.com 21211308Santhony.gutierrez@amd.com Stats::Histogram& 21311308Santhony.gutierrez@amd.com getInitialToForwardDelayHist(const MachineType t) const 21411308Santhony.gutierrez@amd.com { return *m_InitialToForwardDelayHist[t]; } 21511308Santhony.gutierrez@amd.com 21611308Santhony.gutierrez@amd.com Stats::Histogram& 21711308Santhony.gutierrez@amd.com getForwardRequestToFirstResponseHist(const MachineType t) const 21811308Santhony.gutierrez@amd.com { return *m_ForwardToFirstResponseDelayHist[t]; } 21911308Santhony.gutierrez@amd.com 22011308Santhony.gutierrez@amd.com Stats::Histogram& 22111308Santhony.gutierrez@amd.com getFirstResponseToCompletionDelayHist(const MachineType t) const 22211308Santhony.gutierrez@amd.com { return *m_FirstResponseToCompletionDelayHist[t]; } 22311308Santhony.gutierrez@amd.com 22411308Santhony.gutierrez@amd.com // Changed to protected to enable inheritance by VIPER Coalescer 22511308Santhony.gutierrez@amd.com protected: 22611308Santhony.gutierrez@amd.com bool tryCacheAccess(Addr addr, RubyRequestType type, 22711308Santhony.gutierrez@amd.com Addr pc, RubyAccessMode access_mode, 22811308Santhony.gutierrez@amd.com int size, DataBlock*& data_ptr); 22911308Santhony.gutierrez@amd.com // Alternate implementations in VIPER Coalescer 23011308Santhony.gutierrez@amd.com virtual void issueRequest(PacketPtr pkt, RubyRequestType type); 23111308Santhony.gutierrez@amd.com 23211308Santhony.gutierrez@amd.com void kernelCallback(int wavfront_id); 23311308Santhony.gutierrez@amd.com 23411308Santhony.gutierrez@amd.com void hitCallback(GPUCoalescerRequest* request, 23511308Santhony.gutierrez@amd.com MachineType mach, 23611308Santhony.gutierrez@amd.com DataBlock& data, 23711308Santhony.gutierrez@amd.com bool success, 23811308Santhony.gutierrez@amd.com Cycles initialRequestTime, 23911308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 24011308Santhony.gutierrez@amd.com Cycles firstResponseTime, 24111308Santhony.gutierrez@amd.com bool isRegion); 24211308Santhony.gutierrez@amd.com void recordMissLatency(GPUCoalescerRequest* request, 24311308Santhony.gutierrez@amd.com MachineType mach, 24411308Santhony.gutierrez@amd.com Cycles initialRequestTime, 24511308Santhony.gutierrez@amd.com Cycles forwardRequestTime, 24611308Santhony.gutierrez@amd.com Cycles firstResponseTime, 24711308Santhony.gutierrez@amd.com bool success, bool isRegion); 24811308Santhony.gutierrez@amd.com void completeHitCallback(std::vector<PacketPtr> & mylist, int len); 24911308Santhony.gutierrez@amd.com PacketPtr mapAddrToPkt(Addr address); 25011308Santhony.gutierrez@amd.com 25111308Santhony.gutierrez@amd.com 25211308Santhony.gutierrez@amd.com RequestStatus getRequestStatus(PacketPtr pkt, 25311308Santhony.gutierrez@amd.com RubyRequestType request_type); 25411308Santhony.gutierrez@amd.com bool insertRequest(PacketPtr pkt, RubyRequestType request_type); 25511308Santhony.gutierrez@amd.com 25611308Santhony.gutierrez@amd.com bool handleLlsc(Addr address, GPUCoalescerRequest* request); 25711308Santhony.gutierrez@amd.com 25812133Sspwilson2@wisc.edu EventFunctionWrapper issueEvent; 25911308Santhony.gutierrez@amd.com 26011308Santhony.gutierrez@amd.com 26111308Santhony.gutierrez@amd.com // Changed to protected to enable inheritance by VIPER Coalescer 26211308Santhony.gutierrez@amd.com protected: 26311308Santhony.gutierrez@amd.com int m_max_outstanding_requests; 26411308Santhony.gutierrez@amd.com int m_deadlock_threshold; 26511308Santhony.gutierrez@amd.com 26611308Santhony.gutierrez@amd.com CacheMemory* m_dataCache_ptr; 26711308Santhony.gutierrez@amd.com CacheMemory* m_instCache_ptr; 26811308Santhony.gutierrez@amd.com 26911308Santhony.gutierrez@amd.com // The cache access latency for this GPU data cache. This is assessed at the 27011308Santhony.gutierrez@amd.com // beginning of each access. This should be very similar to the 27111308Santhony.gutierrez@amd.com // implementation in Sequencer() as this is very much like a Sequencer 27211308Santhony.gutierrez@amd.com Cycles m_data_cache_hit_latency; 27311308Santhony.gutierrez@amd.com 27411308Santhony.gutierrez@amd.com // We need to track both the primary and secondary request types. 27511308Santhony.gutierrez@amd.com // The secondary request type comprises a subset of RubyRequestTypes that 27611308Santhony.gutierrez@amd.com // are understood by the L1 Controller. A primary request type can be any 27711308Santhony.gutierrez@amd.com // RubyRequestType. 27811689Santhony.gutierrez@amd.com typedef std::unordered_map<Addr, std::vector<RequestDesc>> CoalescingTable; 27911308Santhony.gutierrez@amd.com CoalescingTable reqCoalescer; 28011308Santhony.gutierrez@amd.com std::vector<Addr> newRequests; 28111308Santhony.gutierrez@amd.com 28211308Santhony.gutierrez@amd.com typedef std::unordered_map<Addr, GPUCoalescerRequest*> RequestTable; 28311308Santhony.gutierrez@amd.com RequestTable m_writeRequestTable; 28411308Santhony.gutierrez@amd.com RequestTable m_readRequestTable; 28511308Santhony.gutierrez@amd.com // Global outstanding request count, across all request tables 28611308Santhony.gutierrez@amd.com int m_outstanding_count; 28711308Santhony.gutierrez@amd.com bool m_deadlock_check_scheduled; 28811308Santhony.gutierrez@amd.com std::unordered_map<int, PacketPtr> kernelEndList; 28911308Santhony.gutierrez@amd.com std::vector<int> newKernelEnds; 29011308Santhony.gutierrez@amd.com 29111308Santhony.gutierrez@amd.com int m_store_waiting_on_load_cycles; 29211308Santhony.gutierrez@amd.com int m_store_waiting_on_store_cycles; 29311308Santhony.gutierrez@amd.com int m_load_waiting_on_store_cycles; 29411308Santhony.gutierrez@amd.com int m_load_waiting_on_load_cycles; 29511308Santhony.gutierrez@amd.com 29611660Stushar@ece.gatech.edu bool m_runningGarnetStandalone; 29711308Santhony.gutierrez@amd.com 29812133Sspwilson2@wisc.edu EventFunctionWrapper deadlockCheckEvent; 29911308Santhony.gutierrez@amd.com bool assumingRfOCoherence; 30011308Santhony.gutierrez@amd.com 30111308Santhony.gutierrez@amd.com // m5 style stats for TCP hit/miss counts 30211308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCPLdHits; 30311308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCPLdTransfers; 30411308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCCLdHits; 30511308Santhony.gutierrez@amd.com Stats::Scalar GPU_LdMiss; 30611308Santhony.gutierrez@amd.com 30711308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCPStHits; 30811308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCPStTransfers; 30911308Santhony.gutierrez@amd.com Stats::Scalar GPU_TCCStHits; 31011308Santhony.gutierrez@amd.com Stats::Scalar GPU_StMiss; 31111308Santhony.gutierrez@amd.com 31211308Santhony.gutierrez@amd.com Stats::Scalar CP_TCPLdHits; 31311308Santhony.gutierrez@amd.com Stats::Scalar CP_TCPLdTransfers; 31411308Santhony.gutierrez@amd.com Stats::Scalar CP_TCCLdHits; 31511308Santhony.gutierrez@amd.com Stats::Scalar CP_LdMiss; 31611308Santhony.gutierrez@amd.com 31711308Santhony.gutierrez@amd.com Stats::Scalar CP_TCPStHits; 31811308Santhony.gutierrez@amd.com Stats::Scalar CP_TCPStTransfers; 31911308Santhony.gutierrez@amd.com Stats::Scalar CP_TCCStHits; 32011308Santhony.gutierrez@amd.com Stats::Scalar CP_StMiss; 32111308Santhony.gutierrez@amd.com 32211308Santhony.gutierrez@amd.com //! Histogram for number of outstanding requests per cycle. 32311308Santhony.gutierrez@amd.com Stats::Histogram m_outstandReqHist; 32411308Santhony.gutierrez@amd.com 32511308Santhony.gutierrez@amd.com //! Histogram for holding latency profile of all requests. 32611308Santhony.gutierrez@amd.com Stats::Histogram m_latencyHist; 32711308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_typeLatencyHist; 32811308Santhony.gutierrez@amd.com 32911308Santhony.gutierrez@amd.com //! Histogram for holding latency profile of all requests that 33011308Santhony.gutierrez@amd.com //! miss in the controller connected to this sequencer. 33111308Santhony.gutierrez@amd.com Stats::Histogram m_missLatencyHist; 33211308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_missTypeLatencyHist; 33311308Santhony.gutierrez@amd.com 33411308Santhony.gutierrez@amd.com //! Histograms for profiling the latencies for requests that 33511308Santhony.gutierrez@amd.com //! required external messages. 33611308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_missMachLatencyHist; 33711308Santhony.gutierrez@amd.com std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; 33811308Santhony.gutierrez@amd.com 33911308Santhony.gutierrez@amd.com //! Histograms for recording the breakdown of miss latency 34011308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 34111308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 34211308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 34311308Santhony.gutierrez@amd.com std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 34411900Sandreas.sandberg@arm.com 34511900Sandreas.sandberg@arm.comprivate: 34611900Sandreas.sandberg@arm.com // Private copy constructor and assignment operator 34711900Sandreas.sandberg@arm.com GPUCoalescer(const GPUCoalescer& obj); 34811900Sandreas.sandberg@arm.com GPUCoalescer& operator=(const GPUCoalescer& obj); 34911308Santhony.gutierrez@amd.com}; 35011308Santhony.gutierrez@amd.com 35111308Santhony.gutierrez@amd.cominline std::ostream& 35211308Santhony.gutierrez@amd.comoperator<<(std::ostream& out, const GPUCoalescer& obj) 35311308Santhony.gutierrez@amd.com{ 35411308Santhony.gutierrez@amd.com obj.print(out); 35511308Santhony.gutierrez@amd.com out << std::flush; 35611308Santhony.gutierrez@amd.com return out; 35711308Santhony.gutierrez@amd.com} 35811308Santhony.gutierrez@amd.com 35911308Santhony.gutierrez@amd.com#endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__ 360