DMASequencer.hh revision 6285:ce086eca1ede
12315SN/A 22332SN/A#ifndef DMASEQUENCER_H 32315SN/A#define DMASEQUENCER_H 42315SN/A 52315SN/A#include <ostream> 62315SN/A#include "mem/ruby/common/DataBlock.hh" 72315SN/A#include "mem/ruby/system/RubyPort.hh" 82315SN/A 92315SN/Astruct DMARequest { 102315SN/A uint64_t start_paddr; 112315SN/A int len; 122315SN/A bool write; 132315SN/A int bytes_completed; 142315SN/A int bytes_issued; 152315SN/A uint8* data; 162315SN/A int64_t id; 172315SN/A}; 182315SN/A 192315SN/Aclass MessageBuffer; 202315SN/Aclass AbstractController; 212315SN/A 222315SN/Aclass DMASequencer :public RubyPort { 232315SN/Apublic: 242315SN/A DMASequencer(const string & name); 252315SN/A void init(const vector<string> & argv); 262315SN/A /* external interface */ 272689SN/A int64_t makeRequest(const RubyRequest & request); 282689SN/A // void issueRequest(uint64_t paddr, uint8* data, int len, bool rw); 292315SN/A bool busy() { return m_is_busy;} 302315SN/A 312315SN/A /* SLICC callback */ 322315SN/A void dataCallback(const DataBlock & dblk); 332315SN/A void ackCallback(); 342315SN/A 356658Snate@binkert.org void printConfig(std::ostream & out); 362315SN/A 372315SN/Aprivate: 382683SN/A void issueNext(); 392680SN/A 402315SN/Aprivate: 412315SN/A int m_version; 422315SN/A AbstractController* m_controller; 432315SN/A bool m_is_busy; 442315SN/A DMARequest active_request; 452315SN/A int num_active_requests; 462315SN/A MessageBuffer* m_mandatory_q_ptr; 472315SN/A}; 482315SN/A 492315SN/A#endif // DMACONTROLLER_H 502315SN/A