DMASequencer.hh revision 11108:6342ddf6d733 
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
31
32#include <memory>
33#include <ostream>
34
35#include "mem/mem_object.hh"
36#include "mem/protocol/DMASequencerRequestType.hh"
37#include "mem/protocol/RequestStatus.hh"
38#include "mem/ruby/common/DataBlock.hh"
39#include "mem/ruby/network/MessageBuffer.hh"
40#include "mem/ruby/system/RubySystem.hh"
41#include "mem/simple_mem.hh"
42#include "mem/tport.hh"
43#include "params/DMASequencer.hh"
44
45class AbstractController;
46
47struct DMARequest
48{
49    uint64_t start_paddr;
50    int len;
51    bool write;
52    int bytes_completed;
53    int bytes_issued;
54    uint8_t *data;
55    PacketPtr pkt;
56};
57
58class DMASequencer : public MemObject
59{
60  public:
61    typedef DMASequencerParams Params;
62    DMASequencer(const Params *);
63    void init();
64    RubySystem *m_ruby_system;
65
66  public:
67    class MemSlavePort : public QueuedSlavePort
68    {
69      private:
70        RespPacketQueue queue;
71        RubySystem* m_ruby_system;
72        bool access_backing_store;
73
74      public:
75        MemSlavePort(const std::string &_name, DMASequencer *_port,
76                     PortID id, RubySystem *_ruby_system,
77                     bool _access_backing_store);
78        void hitCallback(PacketPtr pkt);
79        void evictionCallback(Addr address);
80
81      protected:
82        bool recvTimingReq(PacketPtr pkt);
83
84        Tick recvAtomic(PacketPtr pkt)
85        { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); }
86
87        void recvFunctional(PacketPtr pkt)
88        { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); }
89
90        AddrRangeList getAddrRanges() const
91        { AddrRangeList ranges; return ranges; }
92
93      private:
94        bool isPhysMemAddress(Addr addr) const;
95    };
96
97    BaseSlavePort &getSlavePort(const std::string &if_name,
98                                PortID idx = InvalidPortID);
99
100    /* external interface */
101    RequestStatus makeRequest(PacketPtr pkt);
102    bool busy() { return m_is_busy;}
103    int outstandingCount() const { return (m_is_busy ? 1 : 0); }
104    bool isDeadlockEventScheduled() const { return false; }
105    void descheduleDeadlockEvent() {}
106
107    // Called by the controller to give the sequencer a pointer.
108    // A pointer to the controller is needed for atomic support.
109    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
110    uint32_t getId() { return m_version; }
111    DrainState drain() M5_ATTR_OVERRIDE;
112
113    /* SLICC callback */
114    void dataCallback(const DataBlock & dblk);
115    void ackCallback();
116
117    void recordRequestType(DMASequencerRequestType requestType);
118
119  private:
120    void issueNext();
121    void ruby_hit_callback(PacketPtr pkt);
122    void testDrainComplete();
123
124    /**
125     * Called by the PIO port when receiving a timing response.
126     *
127     * @param pkt Response packet
128     * @param master_port_id Port id of the PIO port
129     *
130     * @return Whether successfully sent
131     */
132    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
133    unsigned int getChildDrainCount();
134
135  private:
136    uint32_t m_version;
137    AbstractController* m_controller;
138    MessageBuffer* m_mandatory_q_ptr;
139    bool m_usingRubyTester;
140
141    MemSlavePort slave_port;
142
143    System* system;
144
145    bool retry;
146    bool m_is_busy;
147    uint64_t m_data_block_mask;
148    DMARequest active_request;
149};
150
151#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
152