DMASequencer.hh revision 10706:4206946d60fe 
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
31
32#include <memory>
33#include <ostream>
34
35#include "mem/protocol/DMASequencerRequestType.hh"
36#include "mem/protocol/RequestStatus.hh"
37#include "mem/ruby/common/DataBlock.hh"
38#include "mem/ruby/network/MessageBuffer.hh"
39#include "mem/ruby/system/System.hh"
40#include "mem/mem_object.hh"
41#include "mem/simple_mem.hh"
42#include "mem/tport.hh"
43#include "params/DMASequencer.hh"
44
45class AbstractController;
46
47struct DMARequest
48{
49    uint64_t start_paddr;
50    int len;
51    bool write;
52    int bytes_completed;
53    int bytes_issued;
54    uint8_t *data;
55    PacketPtr pkt;
56};
57
58class DMASequencer : public MemObject
59{
60  public:
61    typedef DMASequencerParams Params;
62    DMASequencer(const Params *);
63    void init();
64
65  public:
66    class MemSlavePort : public QueuedSlavePort
67    {
68      private:
69        SlavePacketQueue queue;
70        RubySystem* ruby_system;
71        bool access_backing_store;
72
73      public:
74        MemSlavePort(const std::string &_name, DMASequencer *_port,
75                     PortID id, RubySystem *_ruby_system,
76                     bool _access_backing_store);
77        void hitCallback(PacketPtr pkt);
78        void evictionCallback(const Address& address);
79
80      protected:
81        bool recvTimingReq(PacketPtr pkt);
82
83        Tick recvAtomic(PacketPtr pkt)
84        { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); }
85
86        void recvFunctional(PacketPtr pkt)
87        { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); }
88
89        AddrRangeList getAddrRanges() const
90        { AddrRangeList ranges; return ranges; }
91
92      private:
93        bool isPhysMemAddress(Addr addr) const;
94    };
95
96    BaseSlavePort &getSlavePort(const std::string &if_name,
97                                PortID idx = InvalidPortID);
98
99    /* external interface */
100    RequestStatus makeRequest(PacketPtr pkt);
101    bool busy() { return m_is_busy;}
102    int outstandingCount() const { return (m_is_busy ? 1 : 0); }
103    bool isDeadlockEventScheduled() const { return false; }
104    void descheduleDeadlockEvent() {}
105
106    // Called by the controller to give the sequencer a pointer.
107    // A pointer to the controller is needed for atomic support.
108    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
109    uint32_t getId() { return m_version; }
110    unsigned int drain(DrainManager *dm);
111
112    /* SLICC callback */
113    void dataCallback(const DataBlock & dblk);
114    void ackCallback();
115
116    void recordRequestType(DMASequencerRequestType requestType);
117
118  private:
119    void issueNext();
120    void ruby_hit_callback(PacketPtr pkt);
121    void testDrainComplete();
122
123    /**
124     * Called by the PIO port when receiving a timing response.
125     *
126     * @param pkt Response packet
127     * @param master_port_id Port id of the PIO port
128     *
129     * @return Whether successfully sent
130     */
131    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
132    unsigned int getChildDrainCount(DrainManager *dm);
133
134  private:
135    uint32_t m_version;
136    AbstractController* m_controller;
137    MessageBuffer* m_mandatory_q_ptr;
138    bool m_usingRubyTester;
139
140    MemSlavePort slave_port;
141
142    DrainManager *drainManager;
143    System* system;
144
145    bool retry;
146    bool m_is_busy;
147    uint64_t m_data_block_mask;
148    DMARequest active_request;
149};
150
151#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
152