DMASequencer.hh revision 11702
17008Snate@binkert.org/*
27008Snate@binkert.org * Copyright (c) 2008 Mark D. Hill and David A. Wood
37008Snate@binkert.org * All rights reserved.
47008Snate@binkert.org *
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97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright
107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
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147008Snate@binkert.org * this software without specific prior written permission.
157008Snate@binkert.org *
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277008Snate@binkert.org */
286285Snate@binkert.org
297039Snate@binkert.org#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
307039Snate@binkert.org#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
316285Snate@binkert.org
3210706Spower.jg@gmail.com#include <memory>
336285Snate@binkert.org#include <ostream>
3411702Smichael.lebeane@amd.com#include <unordered_map>
357039Snate@binkert.org
369104Shestness@cs.utexas.edu#include "mem/protocol/DMASequencerRequestType.hh"
3711702Smichael.lebeane@amd.com#include "mem/ruby/common/Address.hh"
386285Snate@binkert.org#include "mem/ruby/common/DataBlock.hh"
3911339SMichael.Lebeane@amd.com#include "mem/ruby/system/RubyPort.hh"
406876Ssteve.reinhardt@amd.com#include "params/DMASequencer.hh"
416876Ssteve.reinhardt@amd.com
427039Snate@binkert.orgstruct DMARequest
437039Snate@binkert.org{
4411702Smichael.lebeane@amd.com    DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed,
4511702Smichael.lebeane@amd.com               int bytes_issued, uint8_t *data, PacketPtr pkt);
4611702Smichael.lebeane@amd.com
477039Snate@binkert.org    uint64_t start_paddr;
487039Snate@binkert.org    int len;
497039Snate@binkert.org    bool write;
507039Snate@binkert.org    int bytes_completed;
517039Snate@binkert.org    int bytes_issued;
529208Snilay@cs.wisc.edu    uint8_t *data;
537039Snate@binkert.org    PacketPtr pkt;
546285Snate@binkert.org};
556285Snate@binkert.org
5611339SMichael.Lebeane@amd.comclass DMASequencer : public RubyPort
577039Snate@binkert.org{
587039Snate@binkert.org  public:
596876Ssteve.reinhardt@amd.com    typedef DMASequencerParams Params;
607039Snate@binkert.org    DMASequencer(const Params *);
6111169Sandreas.hansson@arm.com    void init() override;
6210518Snilay@cs.wisc.edu
637039Snate@binkert.org    /* external interface */
6411347Sandreas.hansson@arm.com    RequestStatus makeRequest(PacketPtr pkt) override;
6511702Smichael.lebeane@amd.com    bool busy() { return m_outstanding_count > 0; }
6611702Smichael.lebeane@amd.com    int outstandingCount() const override { return m_outstanding_count; }
6711347Sandreas.hansson@arm.com    bool isDeadlockEventScheduled() const override { return false; }
6811347Sandreas.hansson@arm.com    void descheduleDeadlockEvent() override {}
696285Snate@binkert.org
707039Snate@binkert.org    /* SLICC callback */
7111702Smichael.lebeane@amd.com    void dataCallback(const DataBlock &dblk, const Addr &addr);
7211702Smichael.lebeane@amd.com    void ackCallback(const Addr &addr);
736285Snate@binkert.org
749104Shestness@cs.utexas.edu    void recordRequestType(DMASequencerRequestType requestType);
759104Shestness@cs.utexas.edu
767039Snate@binkert.org  private:
7711702Smichael.lebeane@amd.com    void issueNext(const Addr &addr);
7810518Snilay@cs.wisc.edu
797039Snate@binkert.org    uint64_t m_data_block_mask;
8011702Smichael.lebeane@amd.com
8111702Smichael.lebeane@amd.com    typedef std::unordered_map<Addr, DMARequest> RequestTable;
8211702Smichael.lebeane@amd.com    RequestTable m_RequestTable;
8311702Smichael.lebeane@amd.com
8411702Smichael.lebeane@amd.com    int m_outstanding_count;
8511702Smichael.lebeane@amd.com    int m_max_outstanding_requests;
866285Snate@binkert.org};
876285Snate@binkert.org
887039Snate@binkert.org#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
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