DMASequencer.hh revision 10518
112391Sjason@lowepower.com/* 212391Sjason@lowepower.com * Copyright (c) 2008 Mark D. Hill and David A. Wood 312391Sjason@lowepower.com * All rights reserved. 412391Sjason@lowepower.com * 512391Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 612391Sjason@lowepower.com * modification, are permitted provided that the following conditions are 712391Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 812391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 912391Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 1012391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 1112391Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 1212391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 1312391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 1412391Sjason@lowepower.com * this software without specific prior written permission. 1512391Sjason@lowepower.com * 1612391Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712391Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812391Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912391Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012391Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112391Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212391Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312391Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412391Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512391Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612391Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712391Sjason@lowepower.com */ 2812391Sjason@lowepower.com 2912391Sjason@lowepower.com#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 3012391Sjason@lowepower.com#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 3112391Sjason@lowepower.com 3212391Sjason@lowepower.com#include <ostream> 3312391Sjason@lowepower.com#include <memory> 3412391Sjason@lowepower.com 3512391Sjason@lowepower.com#include "mem/protocol/DMASequencerRequestType.hh" 3612391Sjason@lowepower.com#include "mem/protocol/RequestStatus.hh" 3712391Sjason@lowepower.com#include "mem/ruby/common/DataBlock.hh" 3812391Sjason@lowepower.com#include "mem/ruby/network/MessageBuffer.hh" 3912391Sjason@lowepower.com#include "mem/ruby/system/System.hh" 4012391Sjason@lowepower.com#include "mem/mem_object.hh" 4112391Sjason@lowepower.com#include "mem/tport.hh" 4212391Sjason@lowepower.com#include "params/DMASequencer.hh" 4312391Sjason@lowepower.com 4412391Sjason@lowepower.comclass AbstractController; 4512391Sjason@lowepower.com 4612391Sjason@lowepower.comstruct DMARequest 4712391Sjason@lowepower.com{ 4812391Sjason@lowepower.com uint64_t start_paddr; 4912391Sjason@lowepower.com int len; 5012391Sjason@lowepower.com bool write; 5112391Sjason@lowepower.com int bytes_completed; 5212391Sjason@lowepower.com int bytes_issued; 5312391Sjason@lowepower.com uint8_t *data; 5412391Sjason@lowepower.com PacketPtr pkt; 5512391Sjason@lowepower.com}; 5612391Sjason@lowepower.com 5712391Sjason@lowepower.comclass DMASequencer : public MemObject 5812391Sjason@lowepower.com{ 5912391Sjason@lowepower.com public: 6012391Sjason@lowepower.com typedef DMASequencerParams Params; 6112391Sjason@lowepower.com DMASequencer(const Params *); 6212391Sjason@lowepower.com void init(); 6312391Sjason@lowepower.com 6412391Sjason@lowepower.com public: 6512391Sjason@lowepower.com class MemSlavePort : public QueuedSlavePort 6612391Sjason@lowepower.com { 6712391Sjason@lowepower.com private: 6812391Sjason@lowepower.com SlavePacketQueue queue; 6912391Sjason@lowepower.com bool access_phys_mem; 7012391Sjason@lowepower.com 7112391Sjason@lowepower.com public: 7212391Sjason@lowepower.com MemSlavePort(const std::string &_name, DMASequencer *_port, 7312391Sjason@lowepower.com bool _access_phys_mem, PortID id); 7412391Sjason@lowepower.com void hitCallback(PacketPtr pkt); 7512391Sjason@lowepower.com void evictionCallback(const Address& address); 7612391Sjason@lowepower.com 7712391Sjason@lowepower.com protected: 7812391Sjason@lowepower.com bool recvTimingReq(PacketPtr pkt); 7912391Sjason@lowepower.com 8012391Sjason@lowepower.com Tick recvAtomic(PacketPtr pkt) 8112391Sjason@lowepower.com { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); } 8212391Sjason@lowepower.com 8312391Sjason@lowepower.com void recvFunctional(PacketPtr pkt) 8412391Sjason@lowepower.com { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); } 8512391Sjason@lowepower.com 8612391Sjason@lowepower.com AddrRangeList getAddrRanges() const 8712391Sjason@lowepower.com { AddrRangeList ranges; return ranges; } 8812391Sjason@lowepower.com 8912391Sjason@lowepower.com private: 9012391Sjason@lowepower.com bool isPhysMemAddress(Addr addr) const; 9112391Sjason@lowepower.com }; 9212391Sjason@lowepower.com 9312391Sjason@lowepower.com BaseSlavePort &getSlavePort(const std::string &if_name, 9412391Sjason@lowepower.com PortID idx = InvalidPortID); 9512391Sjason@lowepower.com 9612391Sjason@lowepower.com /* external interface */ 9712391Sjason@lowepower.com RequestStatus makeRequest(PacketPtr pkt); 9812391Sjason@lowepower.com bool busy() { return m_is_busy;} 9912391Sjason@lowepower.com int outstandingCount() const { return (m_is_busy ? 1 : 0); } 10012391Sjason@lowepower.com bool isDeadlockEventScheduled() const { return false; } 10112391Sjason@lowepower.com void descheduleDeadlockEvent() {} 10212391Sjason@lowepower.com 10312391Sjason@lowepower.com // Called by the controller to give the sequencer a pointer. 10412391Sjason@lowepower.com // A pointer to the controller is needed for atomic support. 10512391Sjason@lowepower.com void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 10612391Sjason@lowepower.com uint32_t getId() { return m_version; } 10712391Sjason@lowepower.com unsigned int drain(DrainManager *dm); 10812391Sjason@lowepower.com 10912391Sjason@lowepower.com /* SLICC callback */ 11012391Sjason@lowepower.com void dataCallback(const DataBlock & dblk); 11112391Sjason@lowepower.com void ackCallback(); 11212391Sjason@lowepower.com 11312391Sjason@lowepower.com void recordRequestType(DMASequencerRequestType requestType); 11412391Sjason@lowepower.com 11512391Sjason@lowepower.com private: 11612391Sjason@lowepower.com void issueNext(); 11712391Sjason@lowepower.com void ruby_hit_callback(PacketPtr pkt); 11812391Sjason@lowepower.com void testDrainComplete(); 11912391Sjason@lowepower.com 12012391Sjason@lowepower.com /** 12112391Sjason@lowepower.com * Called by the PIO port when receiving a timing response. 12212391Sjason@lowepower.com * 12312391Sjason@lowepower.com * @param pkt Response packet 12412391Sjason@lowepower.com * @param master_port_id Port id of the PIO port 12512391Sjason@lowepower.com * 12612391Sjason@lowepower.com * @return Whether successfully sent 12712391Sjason@lowepower.com */ 12812391Sjason@lowepower.com bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 12912391Sjason@lowepower.com unsigned int getChildDrainCount(DrainManager *dm); 13012391Sjason@lowepower.com 13112391Sjason@lowepower.com private: 13212391Sjason@lowepower.com uint32_t m_version; 13312391Sjason@lowepower.com AbstractController* m_controller; 13412391Sjason@lowepower.com MessageBuffer* m_mandatory_q_ptr; 13512391Sjason@lowepower.com bool m_usingRubyTester; 13612391Sjason@lowepower.com 13712391Sjason@lowepower.com MemSlavePort slave_port; 13812391Sjason@lowepower.com 13912391Sjason@lowepower.com DrainManager *drainManager; 14012391Sjason@lowepower.com System* system; 14112391Sjason@lowepower.com 14212391Sjason@lowepower.com bool retry; 14312391Sjason@lowepower.com bool access_phys_mem; 14412391Sjason@lowepower.com 14512391Sjason@lowepower.com bool m_is_busy; 14612391Sjason@lowepower.com uint64_t m_data_block_mask; 14712391Sjason@lowepower.com DMARequest active_request; 14812391Sjason@lowepower.com}; 14912391Sjason@lowepower.com 15012391Sjason@lowepower.com#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 15112391Sjason@lowepower.com