DMASequencer.cc revision 9466:23e13ad7091f
16332Sgblack@eecs.umich.edu/* 26332Sgblack@eecs.umich.edu * Copyright (c) 2008 Mark D. Hill and David A. Wood 36332Sgblack@eecs.umich.edu * All rights reserved. 46332Sgblack@eecs.umich.edu * 56332Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66332Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76332Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86332Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96332Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106332Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116332Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126332Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136332Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146332Sgblack@eecs.umich.edu * this software without specific prior written permission. 156332Sgblack@eecs.umich.edu * 166332Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176332Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186332Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196332Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206332Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216332Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226332Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236332Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246332Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256332Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266332Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276332Sgblack@eecs.umich.edu */ 286332Sgblack@eecs.umich.edu 296332Sgblack@eecs.umich.edu#include "debug/RubyDma.hh" 306332Sgblack@eecs.umich.edu#include "debug/RubyStats.hh" 316332Sgblack@eecs.umich.edu#include "mem/protocol/SequencerMsg.hh" 326332Sgblack@eecs.umich.edu#include "mem/protocol/SequencerRequestType.hh" 336332Sgblack@eecs.umich.edu#include "mem/ruby/buffers/MessageBuffer.hh" 346332Sgblack@eecs.umich.edu#include "mem/ruby/system/DMASequencer.hh" 356332Sgblack@eecs.umich.edu#include "mem/ruby/system/System.hh" 366332Sgblack@eecs.umich.edu 376332Sgblack@eecs.umich.eduDMASequencer::DMASequencer(const Params *p) 386332Sgblack@eecs.umich.edu : RubyPort(p) 396332Sgblack@eecs.umich.edu{ 406332Sgblack@eecs.umich.edu} 416332Sgblack@eecs.umich.edu 426332Sgblack@eecs.umich.eduvoid 436332Sgblack@eecs.umich.eduDMASequencer::init() 446332Sgblack@eecs.umich.edu{ 456332Sgblack@eecs.umich.edu RubyPort::init(); 466332Sgblack@eecs.umich.edu m_is_busy = false; 476332Sgblack@eecs.umich.edu m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 486332Sgblack@eecs.umich.edu} 496332Sgblack@eecs.umich.edu 506332Sgblack@eecs.umich.eduRequestStatus 516332Sgblack@eecs.umich.eduDMASequencer::makeRequest(PacketPtr pkt) 526332Sgblack@eecs.umich.edu{ 53 if (m_is_busy) { 54 return RequestStatus_BufferFull; 55 } 56 57 uint64_t paddr = pkt->getAddr(); 58 uint8_t* data = pkt->getPtr<uint8_t>(true); 59 int len = pkt->getSize(); 60 bool write = pkt->isWrite(); 61 62 assert(!m_is_busy); // only support one outstanding DMA request 63 m_is_busy = true; 64 65 active_request.start_paddr = paddr; 66 active_request.write = write; 67 active_request.data = data; 68 active_request.len = len; 69 active_request.bytes_completed = 0; 70 active_request.bytes_issued = 0; 71 active_request.pkt = pkt; 72 73 SequencerMsg *msg = new SequencerMsg(curCycle()); 74 msg->getPhysicalAddress() = Address(paddr); 75 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 76 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 77 int offset = paddr & m_data_block_mask; 78 79 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 80 len : RubySystem::getBlockSizeBytes() - offset; 81 82 if (write && (data != NULL)) { 83 if (active_request.data != NULL) { 84 msg->getDataBlk().setData(data, offset, msg->getLen()); 85 } 86 } 87 88 assert(m_mandatory_q_ptr != NULL); 89 m_mandatory_q_ptr->enqueue(msg); 90 active_request.bytes_issued += msg->getLen(); 91 92 return RequestStatus_Issued; 93} 94 95void 96DMASequencer::issueNext() 97{ 98 assert(m_is_busy == true); 99 active_request.bytes_completed = active_request.bytes_issued; 100 if (active_request.len == active_request.bytes_completed) { 101 // 102 // Must unset the busy flag before calling back the dma port because 103 // the callback may cause a previously nacked request to be reissued 104 // 105 DPRINTF(RubyDma, "DMA request completed\n"); 106 m_is_busy = false; 107 ruby_hit_callback(active_request.pkt); 108 return; 109 } 110 111 SequencerMsg *msg = new SequencerMsg(curCycle()); 112 msg->getPhysicalAddress() = Address(active_request.start_paddr + 113 active_request.bytes_completed); 114 115 assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0); 116 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 117 118 msg->getType() = (active_request.write ? SequencerRequestType_ST : 119 SequencerRequestType_LD); 120 121 msg->getLen() = 122 (active_request.len - 123 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 124 active_request.len - active_request.bytes_completed : 125 RubySystem::getBlockSizeBytes()); 126 127 if (active_request.write) { 128 msg->getDataBlk(). 129 setData(&active_request.data[active_request.bytes_completed], 130 0, msg->getLen()); 131 msg->getType() = SequencerRequestType_ST; 132 } else { 133 msg->getType() = SequencerRequestType_LD; 134 } 135 136 assert(m_mandatory_q_ptr != NULL); 137 m_mandatory_q_ptr->enqueue(msg); 138 active_request.bytes_issued += msg->getLen(); 139 DPRINTF(RubyDma, 140 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 141 active_request.bytes_issued, active_request.bytes_completed, 142 active_request.len); 143} 144 145void 146DMASequencer::dataCallback(const DataBlock & dblk) 147{ 148 assert(m_is_busy == true); 149 int len = active_request.bytes_issued - active_request.bytes_completed; 150 int offset = 0; 151 if (active_request.bytes_completed == 0) 152 offset = active_request.start_paddr & m_data_block_mask; 153 assert(active_request.write == false); 154 if (active_request.data != NULL) { 155 memcpy(&active_request.data[active_request.bytes_completed], 156 dblk.getData(offset, len), len); 157 } 158 issueNext(); 159} 160 161void 162DMASequencer::ackCallback() 163{ 164 issueNext(); 165} 166 167void 168DMASequencer::recordRequestType(DMASequencerRequestType requestType) { 169 DPRINTF(RubyStats, "Recorded statistic: %s\n", 170 DMASequencerRequestType_to_string(requestType)); 171} 172 173DMASequencer * 174DMASequencerParams::create() 175{ 176 return new DMASequencer(this); 177} 178