DMASequencer.cc revision 7544:90c5eb6a5e66
1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "mem/protocol/SequencerMsg.hh" 30#include "mem/protocol/SequencerRequestType.hh" 31#include "mem/ruby/buffers/MessageBuffer.hh" 32#include "mem/ruby/slicc_interface/AbstractController.hh" 33#include "mem/ruby/system/DMASequencer.hh" 34#include "mem/ruby/system/System.hh" 35 36DMASequencer::DMASequencer(const Params *p) 37 : RubyPort(p) 38{ 39} 40 41void 42DMASequencer::init() 43{ 44 RubyPort::init(); 45 m_is_busy = false; 46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 47} 48 49RequestStatus 50DMASequencer::makeRequest(const RubyRequest &request) 51{ 52 if (m_is_busy) { 53 return RequestStatus_BufferFull; 54 } 55 56 uint64_t paddr = request.paddr; 57 uint8_t* data = request.data; 58 int len = request.len; 59 bool write = false; 60 switch(request.type) { 61 case RubyRequestType_LD: 62 write = false; 63 break; 64 case RubyRequestType_ST: 65 write = true; 66 break; 67 case RubyRequestType_NULL: 68 case RubyRequestType_IFETCH: 69 case RubyRequestType_Locked_Read: 70 case RubyRequestType_Locked_Write: 71 case RubyRequestType_RMW_Read: 72 case RubyRequestType_RMW_Write: 73 case RubyRequestType_NUM: 74 panic("DMASequencer::makeRequest does not support RubyRequestType"); 75 return RequestStatus_NULL; 76 } 77 78 assert(!m_is_busy); // only support one outstanding DMA request 79 m_is_busy = true; 80 81 active_request.start_paddr = paddr; 82 active_request.write = write; 83 active_request.data = data; 84 active_request.len = len; 85 active_request.bytes_completed = 0; 86 active_request.bytes_issued = 0; 87 active_request.pkt = request.pkt; 88 89 SequencerMsg *msg = new SequencerMsg; 90 msg->getPhysicalAddress() = Address(paddr); 91 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 92 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 93 int offset = paddr & m_data_block_mask; 94 95 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 96 len : RubySystem::getBlockSizeBytes() - offset; 97 98 if (write) { 99 msg->getDataBlk().setData(data, offset, msg->getLen()); 100 } 101 102 assert(m_mandatory_q_ptr != NULL); 103 m_mandatory_q_ptr->enqueue(msg); 104 active_request.bytes_issued += msg->getLen(); 105 106 return RequestStatus_Issued; 107} 108 109void 110DMASequencer::issueNext() 111{ 112 assert(m_is_busy == true); 113 active_request.bytes_completed = active_request.bytes_issued; 114 if (active_request.len == active_request.bytes_completed) { 115 DPRINTF(RubyDma, "DMA request completed\n"); 116 ruby_hit_callback(active_request.pkt); 117 m_is_busy = false; 118 return; 119 } 120 121 SequencerMsg *msg = new SequencerMsg; 122 msg->getPhysicalAddress() = Address(active_request.start_paddr + 123 active_request.bytes_completed); 124 125 assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0); 126 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 127 128 msg->getType() = (active_request.write ? SequencerRequestType_ST : 129 SequencerRequestType_LD); 130 131 msg->getLen() = 132 (active_request.len - 133 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 134 active_request.len - active_request.bytes_completed : 135 RubySystem::getBlockSizeBytes()); 136 137 if (active_request.write) { 138 msg->getDataBlk(). 139 setData(&active_request.data[active_request.bytes_completed], 140 0, msg->getLen()); 141 msg->getType() = SequencerRequestType_ST; 142 } else { 143 msg->getType() = SequencerRequestType_LD; 144 } 145 146 assert(m_mandatory_q_ptr != NULL); 147 m_mandatory_q_ptr->enqueue(msg); 148 active_request.bytes_issued += msg->getLen(); 149 DPRINTF(RubyDma, "Next DMA segment issued to the DMA cntrl\n"); 150} 151 152void 153DMASequencer::dataCallback(const DataBlock & dblk) 154{ 155 assert(m_is_busy == true); 156 int len = active_request.bytes_issued - active_request.bytes_completed; 157 int offset = 0; 158 if (active_request.bytes_completed == 0) 159 offset = active_request.start_paddr & m_data_block_mask; 160 assert(active_request.write == false); 161 memcpy(&active_request.data[active_request.bytes_completed], 162 dblk.getData(offset, len), len); 163 issueNext(); 164} 165 166void 167DMASequencer::ackCallback() 168{ 169 issueNext(); 170} 171 172void 173DMASequencer::printConfig(std::ostream & out) 174{ 175} 176 177DMASequencer * 178DMASequencerParams::create() 179{ 180 return new DMASequencer(this); 181} 182