DMASequencer.cc revision 7055
1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "mem/protocol/SequencerMsg.hh" 30#include "mem/protocol/SequencerRequestType.hh" 31#include "mem/ruby/buffers/MessageBuffer.hh" 32#include "mem/ruby/slicc_interface/AbstractController.hh" 33#include "mem/ruby/system/DMASequencer.hh" 34#include "mem/ruby/system/System.hh" 35 36DMASequencer::DMASequencer(const Params *p) 37 : RubyPort(p) 38{ 39} 40 41void 42DMASequencer::init() 43{ 44 RubyPort::init(); 45 m_is_busy = false; 46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 47} 48 49RequestStatus 50DMASequencer::makeRequest(const RubyRequest &request) 51{ 52 uint64_t paddr = request.paddr; 53 uint8_t* data = request.data; 54 int len = request.len; 55 bool write = false; 56 switch(request.type) { 57 case RubyRequestType_LD: 58 write = false; 59 break; 60 case RubyRequestType_ST: 61 write = true; 62 break; 63 case RubyRequestType_NULL: 64 case RubyRequestType_IFETCH: 65 case RubyRequestType_Locked_Read: 66 case RubyRequestType_Locked_Write: 67 case RubyRequestType_RMW_Read: 68 case RubyRequestType_RMW_Write: 69 case RubyRequestType_NUM: 70 panic("DMASequencer::makeRequest does not support RubyRequestType"); 71 return RequestStatus_NULL; 72 } 73 74 assert(!m_is_busy); // only support one outstanding DMA request 75 m_is_busy = true; 76 77 active_request.start_paddr = paddr; 78 active_request.write = write; 79 active_request.data = data; 80 active_request.len = len; 81 active_request.bytes_completed = 0; 82 active_request.bytes_issued = 0; 83 active_request.pkt = request.pkt; 84 85 SequencerMsg msg; 86 msg.getPhysicalAddress() = Address(paddr); 87 msg.getLineAddress() = line_address(msg.getPhysicalAddress()); 88 msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 89 int offset = paddr & m_data_block_mask; 90 91 msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 92 len : RubySystem::getBlockSizeBytes() - offset; 93 94 if (write) { 95 msg.getDataBlk().setData(data, offset, msg.getLen()); 96 } 97 98 assert(m_mandatory_q_ptr != NULL); 99 m_mandatory_q_ptr->enqueue(msg); 100 active_request.bytes_issued += msg.getLen(); 101 102 return RequestStatus_Issued; 103} 104 105void 106DMASequencer::issueNext() 107{ 108 assert(m_is_busy == true); 109 active_request.bytes_completed = active_request.bytes_issued; 110 if (active_request.len == active_request.bytes_completed) { 111 ruby_hit_callback(active_request.pkt); 112 m_is_busy = false; 113 return; 114 } 115 116 SequencerMsg msg; 117 msg.getPhysicalAddress() = Address(active_request.start_paddr + 118 active_request.bytes_completed); 119 120 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); 121 msg.getLineAddress() = line_address(msg.getPhysicalAddress()); 122 123 msg.getType() = (active_request.write ? SequencerRequestType_ST : 124 SequencerRequestType_LD); 125 126 msg.getLen() = 127 (active_request.len - 128 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 129 active_request.len - active_request.bytes_completed : 130 RubySystem::getBlockSizeBytes()); 131 132 if (active_request.write) { 133 msg.getDataBlk(). 134 setData(&active_request.data[active_request.bytes_completed], 135 0, msg.getLen()); 136 msg.getType() = SequencerRequestType_ST; 137 } else { 138 msg.getType() = SequencerRequestType_LD; 139 } 140 141 assert(m_mandatory_q_ptr != NULL); 142 m_mandatory_q_ptr->enqueue(msg); 143 active_request.bytes_issued += msg.getLen(); 144} 145 146void 147DMASequencer::dataCallback(const DataBlock & dblk) 148{ 149 assert(m_is_busy == true); 150 int len = active_request.bytes_issued - active_request.bytes_completed; 151 int offset = 0; 152 if (active_request.bytes_completed == 0) 153 offset = active_request.start_paddr & m_data_block_mask; 154 assert(active_request.write == false); 155 memcpy(&active_request.data[active_request.bytes_completed], 156 dblk.getData(offset, len), len); 157 issueNext(); 158} 159 160void 161DMASequencer::ackCallback() 162{ 163 issueNext(); 164} 165 166void 167DMASequencer::printConfig(std::ostream & out) 168{ 169} 170 171DMASequencer * 172DMASequencerParams::create() 173{ 174 return new DMASequencer(this); 175} 176