DMASequencer.cc revision 6369:82ac95f4d9f0
12SN/A 21762SN/A#include "mem/ruby/system/DMASequencer.hh" 32SN/A#include "mem/ruby/buffers/MessageBuffer.hh" 42SN/A#include "mem/ruby/slicc_interface/AbstractController.hh" 52SN/A 62SN/A/* SLICC generated types */ 72SN/A#include "mem/protocol/DMARequestMsg.hh" 82SN/A#include "mem/protocol/DMARequestType.hh" 92SN/A#include "mem/protocol/DMAResponseMsg.hh" 102SN/A#include "mem/ruby/system/System.hh" 112SN/A 122SN/ADMASequencer::DMASequencer(const string & name) 132SN/A : RubyPort(name) 142SN/A{ 152SN/A} 162SN/A 172SN/Avoid DMASequencer::init(const vector<string> & argv) 182SN/A{ 192SN/A m_version = -1; 202SN/A m_controller = NULL; 212SN/A for (size_t i=0;i<argv.size();i+=2) { 222SN/A if (argv[i] == "controller") 232SN/A m_controller = RubySystem::getController(argv[i+1]); 242SN/A else if (argv[i] == "version") 252SN/A m_version = atoi(argv[i+1].c_str()); 262SN/A } 272665Ssaidi@eecs.umich.edu assert(m_controller != NULL); 282665Ssaidi@eecs.umich.edu assert(m_version != -1); 292665Ssaidi@eecs.umich.edu 302SN/A m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 312SN/A m_is_busy = false; 324183Sgblack@eecs.umich.edu m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 332439SN/A} 342680Sktlim@umich.edu 352222SN/Aint64_t DMASequencer::makeRequest(const RubyRequest & request) 364183Sgblack@eecs.umich.edu{ 374183Sgblack@eecs.umich.edu uint64_t paddr = request.paddr; 384183Sgblack@eecs.umich.edu uint8_t* data = request.data; 392SN/A int len = request.len; 402201SN/A bool write = false; 412680Sktlim@umich.edu switch(request.type) { 422201SN/A case RubyRequestType_LD: 433363Sstever@eecs.umich.edu write = false; 442201SN/A break; 452222SN/A case RubyRequestType_ST: 462680Sktlim@umich.edu write = true; 472222SN/A break; 482680Sktlim@umich.edu case RubyRequestType_NULL: 492680Sktlim@umich.edu case RubyRequestType_IFETCH: 502222SN/A case RubyRequestType_Locked_Read: 512680Sktlim@umich.edu case RubyRequestType_Locked_Write: 522222SN/A case RubyRequestType_RMW_Read: 532201SN/A case RubyRequestType_RMW_Write: 542612SN/A assert(0); 552680Sktlim@umich.edu } 562612SN/A 572612SN/A assert(!m_is_busy); // only support one outstanding DMA request 582612SN/A m_is_busy = true; 594184Ssaidi@eecs.umich.edu 604183Sgblack@eecs.umich.edu active_request.start_paddr = paddr; 614183Sgblack@eecs.umich.edu active_request.write = write; 624183Sgblack@eecs.umich.edu active_request.data = data; 634183Sgblack@eecs.umich.edu active_request.len = len; 644434Ssaidi@eecs.umich.edu active_request.bytes_completed = 0; 654183Sgblack@eecs.umich.edu active_request.bytes_issued = 0; 664434Ssaidi@eecs.umich.edu active_request.id = makeUniqueRequestID(); 674183Sgblack@eecs.umich.edu 684184Ssaidi@eecs.umich.edu DMARequestMsg msg; 69 msg.getPhysicalAddress() = Address(paddr); 70 msg.getLineAddress() = line_address(msg.getPhysicalAddress()); 71 msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ; 72 msg.getOffset() = paddr & m_data_block_mask; 73 msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ? 74 len : 75 RubySystem::getBlockSizeBytes() - msg.getOffset(); 76 if (write) { 77 msg.getType() = DMARequestType_WRITE; 78 msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen()); 79 } else { 80 msg.getType() = DMARequestType_READ; 81 } 82 m_mandatory_q_ptr->enqueue(msg); 83 active_request.bytes_issued += msg.getLen(); 84 85 return active_request.id; 86} 87 88void DMASequencer::issueNext() 89{ 90 assert(m_is_busy == true); 91 active_request.bytes_completed = active_request.bytes_issued; 92 if (active_request.len == active_request.bytes_completed) { 93 m_hit_callback(active_request.id); 94 m_is_busy = false; 95 return; 96 } 97 98 DMARequestMsg msg; 99 msg.getPhysicalAddress() = Address(active_request.start_paddr + 100 active_request.bytes_completed); 101 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); 102 msg.getLineAddress() = line_address(msg.getPhysicalAddress()); 103 msg.getOffset() = 0; 104 msg.getType() = (active_request.write ? DMARequestType_WRITE : 105 DMARequestType_READ); 106 msg.getLen() = (active_request.len - 107 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 108 active_request.len - active_request.bytes_completed : 109 RubySystem::getBlockSizeBytes()); 110 if (active_request.write) { 111 msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 112 0, msg.getLen()); 113 msg.getType() = DMARequestType_WRITE; 114 } else { 115 msg.getType() = DMARequestType_READ; 116 } 117 m_mandatory_q_ptr->enqueue(msg); 118 active_request.bytes_issued += msg.getLen(); 119} 120 121void DMASequencer::dataCallback(const DataBlock & dblk) 122{ 123 assert(m_is_busy == true); 124 int len = active_request.bytes_issued - active_request.bytes_completed; 125 int offset = 0; 126 if (active_request.bytes_completed == 0) 127 offset = active_request.start_paddr & m_data_block_mask; 128 assert( active_request.write == false ); 129 memcpy(&active_request.data[active_request.bytes_completed], 130 dblk.getData(offset, len), len); 131 issueNext(); 132} 133 134void DMASequencer::ackCallback() 135{ 136 issueNext(); 137} 138 139void DMASequencer::printConfig(ostream & out) 140{ 141 142} 143