DMASequencer.cc revision 6350
1 2#include "mem/ruby/system/DMASequencer.hh" 3#include "mem/ruby/buffers/MessageBuffer.hh" 4#include "mem/ruby/slicc_interface/AbstractController.hh" 5 6/* SLICC generated types */ 7#include "mem/protocol/DMARequestMsg.hh" 8#include "mem/protocol/DMARequestType.hh" 9#include "mem/protocol/DMAResponseMsg.hh" 10#include "mem/ruby/system/System.hh" 11 12DMASequencer::DMASequencer(const string & name) 13 : RubyPort(name) 14{ 15} 16 17void DMASequencer::init(const vector<string> & argv) 18{ 19 m_version = -1; 20 m_controller = NULL; 21 for (size_t i=0;i<argv.size();i+=2) { 22 if (argv[i] == "controller") 23 m_controller = RubySystem::getController(argv[i+1]); 24 else if (argv[i] == "version") 25 m_version = atoi(argv[i+1].c_str()); 26 } 27 assert(m_controller != NULL); 28 assert(m_version != -1); 29 30 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 31 m_is_busy = false; 32} 33 34int64_t DMASequencer::makeRequest(const RubyRequest & request) 35{ 36 uint64_t paddr = request.paddr; 37 uint8_t* data = request.data; 38 int len = request.len; 39 bool write = false; 40 switch(request.type) { 41 case RubyRequestType_LD: 42 write = false; 43 break; 44 case RubyRequestType_ST: 45 write = true; 46 break; 47 case RubyRequestType_NULL: 48 case RubyRequestType_IFETCH: 49 case RubyRequestType_Locked_Read: 50 case RubyRequestType_Locked_Write: 51 assert(0); 52 } 53 54 assert(!m_is_busy); 55 m_is_busy = true; 56 57 active_request.start_paddr = paddr; 58 active_request.write = write; 59 active_request.data = data; 60 active_request.len = len; 61 active_request.bytes_completed = 0; 62 active_request.bytes_issued = 0; 63 active_request.id = makeUniqueRequestID(); 64 65 DMARequestMsg msg; 66 msg.getPhysicalAddress() = Address(paddr); 67 msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ; 68 msg.getOffset() = paddr & RubyConfig::dataBlockMask(); 69 msg.getLen() = (msg.getOffset() + len) < RubySystem::getBlockSizeBytes() ? 70 (msg.getOffset() + len) : 71 RubySystem::getBlockSizeBytes() - msg.getOffset(); 72 if (write) { 73 msg.getType() = DMARequestType_WRITE; 74 msg.getDataBlk().setData(data, 0, msg.getLen()); 75 } else { 76 msg.getType() = DMARequestType_READ; 77 } 78 m_mandatory_q_ptr->enqueue(msg); 79 active_request.bytes_issued += msg.getLen(); 80 81 return active_request.id; 82} 83 84void DMASequencer::issueNext() 85{ 86 assert(m_is_busy == true); 87 active_request.bytes_completed = active_request.bytes_issued; 88 if (active_request.len == active_request.bytes_completed) { 89 m_hit_callback(active_request.id); 90 m_is_busy = false; 91 return; 92 } 93 94 DMARequestMsg msg; 95 msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed); 96 assert((msg.getPhysicalAddress().getAddress() & RubyConfig::dataBlockMask()) == 0); 97 msg.getOffset() = 0; 98 msg.getType() = active_request.write ? DMARequestType_WRITE : DMARequestType_READ; 99 msg.getLen() = active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 100 active_request.len - active_request.bytes_completed : 101 RubySystem::getBlockSizeBytes(); 102 if (active_request.write) { 103 msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen()); 104 msg.getType() = DMARequestType_WRITE; 105 } else { 106 msg.getType() = DMARequestType_READ; 107 } 108 m_mandatory_q_ptr->enqueue(msg); 109 active_request.bytes_issued += msg.getLen(); 110} 111 112void DMASequencer::dataCallback(const DataBlock & dblk) 113{ 114 assert(m_is_busy == true); 115 int len = active_request.bytes_issued - active_request.bytes_completed; 116 int offset = 0; 117 if (active_request.bytes_completed == 0) 118 offset = active_request.start_paddr & RubyConfig::dataBlockMask(); 119 memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len); 120 issueNext(); 121} 122 123void DMASequencer::ackCallback() 124{ 125 issueNext(); 126} 127 128void DMASequencer::printConfig(ostream & out) 129{ 130 131} 132