DMASequencer.cc revision 11025:4872dbdea907
110428Sandreas.hansson@arm.com/* 210428Sandreas.hansson@arm.com * Copyright (c) 2008 Mark D. Hill and David A. Wood 310428Sandreas.hansson@arm.com * All rights reserved. 410428Sandreas.hansson@arm.com * 510428Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 610428Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 710428Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 810428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 910428Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1010428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1110428Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1210428Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1310428Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 1410428Sandreas.hansson@arm.com * this software without specific prior written permission. 1510428Sandreas.hansson@arm.com * 1610428Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710428Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810428Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910428Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010428Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110428Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210428Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310428Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410428Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510428Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610428Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710428Sandreas.hansson@arm.com */ 2810428Sandreas.hansson@arm.com 2910428Sandreas.hansson@arm.com#include <memory> 3010428Sandreas.hansson@arm.com 3110428Sandreas.hansson@arm.com#include "debug/Config.hh" 3210428Sandreas.hansson@arm.com#include "debug/Drain.hh" 3310428Sandreas.hansson@arm.com#include "debug/RubyDma.hh" 3410428Sandreas.hansson@arm.com#include "debug/RubyStats.hh" 3510428Sandreas.hansson@arm.com#include "mem/protocol/SequencerMsg.hh" 3610428Sandreas.hansson@arm.com#include "mem/ruby/system/DMASequencer.hh" 3710428Sandreas.hansson@arm.com#include "mem/ruby/system/System.hh" 3810428Sandreas.hansson@arm.com#include "sim/system.hh" 3910428Sandreas.hansson@arm.com 4010428Sandreas.hansson@arm.comDMASequencer::DMASequencer(const Params *p) 4110428Sandreas.hansson@arm.com : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), 4210428Sandreas.hansson@arm.com m_controller(NULL), m_mandatory_q_ptr(NULL), 4310428Sandreas.hansson@arm.com m_usingRubyTester(p->using_ruby_tester), 4410428Sandreas.hansson@arm.com slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system, 4510428Sandreas.hansson@arm.com p->ruby_system->getAccessBackingStore()), 4610428Sandreas.hansson@arm.com system(p->system), retry(false) 4710428Sandreas.hansson@arm.com{ 4810428Sandreas.hansson@arm.com assert(m_version != -1); 4910428Sandreas.hansson@arm.com} 5010428Sandreas.hansson@arm.com 5110428Sandreas.hansson@arm.comvoid 5210428Sandreas.hansson@arm.comDMASequencer::init() 5310428Sandreas.hansson@arm.com{ 5410428Sandreas.hansson@arm.com MemObject::init(); 5510428Sandreas.hansson@arm.com assert(m_controller != NULL); 5610428Sandreas.hansson@arm.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 5710428Sandreas.hansson@arm.com m_mandatory_q_ptr->setSender(this); 5810428Sandreas.hansson@arm.com m_is_busy = false; 5910428Sandreas.hansson@arm.com m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 6010428Sandreas.hansson@arm.com 6110428Sandreas.hansson@arm.com slave_port.sendRangeChange(); 6210428Sandreas.hansson@arm.com} 6310428Sandreas.hansson@arm.com 6410428Sandreas.hansson@arm.comBaseSlavePort & 6510428Sandreas.hansson@arm.comDMASequencer::getSlavePort(const std::string &if_name, PortID idx) 6610428Sandreas.hansson@arm.com{ 6710428Sandreas.hansson@arm.com // used by the CPUs to connect the caches to the interconnect, and 6810428Sandreas.hansson@arm.com // for the x86 case also the interrupt master 6910428Sandreas.hansson@arm.com if (if_name != "slave") { 7010428Sandreas.hansson@arm.com // pass it along to our super class 7110428Sandreas.hansson@arm.com return MemObject::getSlavePort(if_name, idx); 7210428Sandreas.hansson@arm.com } else { 7310428Sandreas.hansson@arm.com return slave_port; 7410428Sandreas.hansson@arm.com } 7510428Sandreas.hansson@arm.com} 7610428Sandreas.hansson@arm.com 7710428Sandreas.hansson@arm.comDMASequencer::MemSlavePort::MemSlavePort(const std::string &_name, 7810428Sandreas.hansson@arm.com DMASequencer *_port, PortID id, RubySystem* _ruby_system, 7910428Sandreas.hansson@arm.com bool _access_backing_store) 8010428Sandreas.hansson@arm.com : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 8110428Sandreas.hansson@arm.com m_ruby_system(_ruby_system), access_backing_store(_access_backing_store) 8210428Sandreas.hansson@arm.com{ 8310428Sandreas.hansson@arm.com DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name); 8410428Sandreas.hansson@arm.com} 8510428Sandreas.hansson@arm.com 8610428Sandreas.hansson@arm.combool 8710428Sandreas.hansson@arm.comDMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt) 8810428Sandreas.hansson@arm.com{ 8910428Sandreas.hansson@arm.com DPRINTF(RubyDma, "Timing request for address %#x on port %d\n", 9010428Sandreas.hansson@arm.com pkt->getAddr(), id); 9110428Sandreas.hansson@arm.com DMASequencer *seq = static_cast<DMASequencer *>(&owner); 9210428Sandreas.hansson@arm.com 9310428Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) 9410428Sandreas.hansson@arm.com panic("DMASequencer should never see an inhibited request\n"); 9510428Sandreas.hansson@arm.com 9610428Sandreas.hansson@arm.com assert(isPhysMemAddress(pkt->getAddr())); 9710428Sandreas.hansson@arm.com assert(getOffset(pkt->getAddr()) + pkt->getSize() <= 9810428Sandreas.hansson@arm.com RubySystem::getBlockSizeBytes()); 9910428Sandreas.hansson@arm.com 10010428Sandreas.hansson@arm.com // Submit the ruby request 10110428Sandreas.hansson@arm.com RequestStatus requestStatus = seq->makeRequest(pkt); 10210428Sandreas.hansson@arm.com 10310428Sandreas.hansson@arm.com // If the request successfully issued then we should return true. 10410428Sandreas.hansson@arm.com // Otherwise, we need to tell the port to retry at a later point 10510428Sandreas.hansson@arm.com // and return false. 10610428Sandreas.hansson@arm.com if (requestStatus == RequestStatus_Issued) { 10710428Sandreas.hansson@arm.com DPRINTF(RubyDma, "Request %s 0x%x issued\n", pkt->cmdString(), 10810428Sandreas.hansson@arm.com pkt->getAddr()); 10910428Sandreas.hansson@arm.com return true; 11010428Sandreas.hansson@arm.com } 11110428Sandreas.hansson@arm.com 11210428Sandreas.hansson@arm.com // Unless one is using the ruby tester, record the stalled M5 port for 11310428Sandreas.hansson@arm.com // later retry when the sequencer becomes free. 11410428Sandreas.hansson@arm.com if (!seq->m_usingRubyTester) { 11510428Sandreas.hansson@arm.com seq->retry = true; 11610428Sandreas.hansson@arm.com } 11710428Sandreas.hansson@arm.com 11810428Sandreas.hansson@arm.com DPRINTF(RubyDma, "Request for address %#x did not issued because %s\n", 11910428Sandreas.hansson@arm.com pkt->getAddr(), RequestStatus_to_string(requestStatus)); 12010428Sandreas.hansson@arm.com 12110428Sandreas.hansson@arm.com return false; 12210428Sandreas.hansson@arm.com} 12310428Sandreas.hansson@arm.com 12410428Sandreas.hansson@arm.comvoid 12510428Sandreas.hansson@arm.comDMASequencer::ruby_hit_callback(PacketPtr pkt) 12610428Sandreas.hansson@arm.com{ 12710428Sandreas.hansson@arm.com DPRINTF(RubyDma, "Hit callback for %s 0x%x\n", pkt->cmdString(), 12810428Sandreas.hansson@arm.com pkt->getAddr()); 12910428Sandreas.hansson@arm.com 13010428Sandreas.hansson@arm.com // The packet was destined for memory and has not yet been turned 13110428Sandreas.hansson@arm.com // into a response 13210428Sandreas.hansson@arm.com assert(system->isMemAddr(pkt->getAddr())); 13310428Sandreas.hansson@arm.com assert(pkt->isRequest()); 13410428Sandreas.hansson@arm.com slave_port.hitCallback(pkt); 13510428Sandreas.hansson@arm.com 13610428Sandreas.hansson@arm.com // If we had to stall the slave ports, wake it up because 13710428Sandreas.hansson@arm.com // the sequencer likely has free resources now. 13810428Sandreas.hansson@arm.com if (retry) { 13910428Sandreas.hansson@arm.com retry = false; 14010428Sandreas.hansson@arm.com DPRINTF(RubyDma,"Sequencer may now be free. SendRetry to port %s\n", 14110428Sandreas.hansson@arm.com slave_port.name()); 14210428Sandreas.hansson@arm.com slave_port.sendRetryReq(); 14310428Sandreas.hansson@arm.com } 14410428Sandreas.hansson@arm.com 14510428Sandreas.hansson@arm.com testDrainComplete(); 14610428Sandreas.hansson@arm.com} 14710428Sandreas.hansson@arm.com 14810428Sandreas.hansson@arm.comvoid 14910428Sandreas.hansson@arm.comDMASequencer::testDrainComplete() 15010428Sandreas.hansson@arm.com{ 15110428Sandreas.hansson@arm.com //If we weren't able to drain before, we might be able to now. 15210428Sandreas.hansson@arm.com if (drainState() == DrainState::Draining) { 15310428Sandreas.hansson@arm.com unsigned int drainCount = outstandingCount(); 15410428Sandreas.hansson@arm.com DPRINTF(Drain, "Drain count: %u\n", drainCount); 15510428Sandreas.hansson@arm.com if (drainCount == 0) { 15610428Sandreas.hansson@arm.com DPRINTF(Drain, "DMASequencer done draining, signaling drain done\n"); 15710428Sandreas.hansson@arm.com signalDrainDone(); 15810428Sandreas.hansson@arm.com } 15910428Sandreas.hansson@arm.com } 16010428Sandreas.hansson@arm.com} 16110428Sandreas.hansson@arm.com 16210490Sandreas.hansson@arm.comDrainState 16310428Sandreas.hansson@arm.comDMASequencer::drain() 16410428Sandreas.hansson@arm.com{ 16510428Sandreas.hansson@arm.com if (isDeadlockEventScheduled()) { 16610428Sandreas.hansson@arm.com descheduleDeadlockEvent(); 16710428Sandreas.hansson@arm.com } 16810428Sandreas.hansson@arm.com 16910428Sandreas.hansson@arm.com // If the DMASequencer is not empty, then it needs to clear all outstanding 17010428Sandreas.hansson@arm.com // requests before it should call signalDrainDone() 17110428Sandreas.hansson@arm.com DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 172 173 // Set status 174 if (outstandingCount() > 0) { 175 DPRINTF(Drain, "DMASequencer not drained\n"); 176 return DrainState::Draining; 177 } else { 178 return DrainState::Drained; 179 } 180} 181 182void 183DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt) 184{ 185 bool needsResponse = pkt->needsResponse(); 186 assert(!pkt->isLLSC()); 187 assert(!pkt->isFlush()); 188 189 DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse); 190 191 // turn packet around to go back to requester if response expected 192 193 if (access_backing_store) { 194 m_ruby_system->getPhysMem()->access(pkt); 195 } else if (needsResponse) { 196 pkt->makeResponse(); 197 } 198 199 if (needsResponse) { 200 DPRINTF(RubyDma, "Sending packet back over port\n"); 201 // send next cycle 202 DMASequencer *seq = static_cast<DMASequencer *>(&owner); 203 RubySystem *rs = seq->m_ruby_system; 204 schedTimingResp(pkt, curTick() + rs->clockPeriod()); 205 } else { 206 delete pkt; 207 } 208 209 DPRINTF(RubyDma, "Hit callback done!\n"); 210} 211 212bool 213DMASequencer::MemSlavePort::isPhysMemAddress(Addr addr) const 214{ 215 DMASequencer *seq = static_cast<DMASequencer *>(&owner); 216 return seq->system->isMemAddr(addr); 217} 218 219RequestStatus 220DMASequencer::makeRequest(PacketPtr pkt) 221{ 222 if (m_is_busy) { 223 return RequestStatus_BufferFull; 224 } 225 226 Addr paddr = pkt->getAddr(); 227 uint8_t* data = pkt->getPtr<uint8_t>(); 228 int len = pkt->getSize(); 229 bool write = pkt->isWrite(); 230 231 assert(!m_is_busy); // only support one outstanding DMA request 232 m_is_busy = true; 233 234 active_request.start_paddr = paddr; 235 active_request.write = write; 236 active_request.data = data; 237 active_request.len = len; 238 active_request.bytes_completed = 0; 239 active_request.bytes_issued = 0; 240 active_request.pkt = pkt; 241 242 std::shared_ptr<SequencerMsg> msg = 243 std::make_shared<SequencerMsg>(clockEdge()); 244 msg->getPhysicalAddress() = paddr; 245 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 246 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 247 int offset = paddr & m_data_block_mask; 248 249 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 250 len : RubySystem::getBlockSizeBytes() - offset; 251 252 if (write && (data != NULL)) { 253 if (active_request.data != NULL) { 254 msg->getDataBlk().setData(data, offset, msg->getLen()); 255 } 256 } 257 258 assert(m_mandatory_q_ptr != NULL); 259 m_mandatory_q_ptr->enqueue(msg); 260 active_request.bytes_issued += msg->getLen(); 261 262 return RequestStatus_Issued; 263} 264 265void 266DMASequencer::issueNext() 267{ 268 assert(m_is_busy); 269 active_request.bytes_completed = active_request.bytes_issued; 270 if (active_request.len == active_request.bytes_completed) { 271 // 272 // Must unset the busy flag before calling back the dma port because 273 // the callback may cause a previously nacked request to be reissued 274 // 275 DPRINTF(RubyDma, "DMA request completed\n"); 276 m_is_busy = false; 277 ruby_hit_callback(active_request.pkt); 278 return; 279 } 280 281 std::shared_ptr<SequencerMsg> msg = 282 std::make_shared<SequencerMsg>(clockEdge()); 283 msg->getPhysicalAddress() = active_request.start_paddr + 284 active_request.bytes_completed; 285 286 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 287 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 288 289 msg->getType() = (active_request.write ? SequencerRequestType_ST : 290 SequencerRequestType_LD); 291 292 msg->getLen() = 293 (active_request.len - 294 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 295 active_request.len - active_request.bytes_completed : 296 RubySystem::getBlockSizeBytes()); 297 298 if (active_request.write) { 299 msg->getDataBlk(). 300 setData(&active_request.data[active_request.bytes_completed], 301 0, msg->getLen()); 302 } 303 304 assert(m_mandatory_q_ptr != NULL); 305 m_mandatory_q_ptr->enqueue(msg); 306 active_request.bytes_issued += msg->getLen(); 307 DPRINTF(RubyDma, 308 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 309 active_request.bytes_issued, active_request.bytes_completed, 310 active_request.len); 311} 312 313void 314DMASequencer::dataCallback(const DataBlock & dblk) 315{ 316 assert(m_is_busy); 317 int len = active_request.bytes_issued - active_request.bytes_completed; 318 int offset = 0; 319 if (active_request.bytes_completed == 0) 320 offset = active_request.start_paddr & m_data_block_mask; 321 assert(!active_request.write); 322 if (active_request.data != NULL) { 323 memcpy(&active_request.data[active_request.bytes_completed], 324 dblk.getData(offset, len), len); 325 } 326 issueNext(); 327} 328 329void 330DMASequencer::ackCallback() 331{ 332 issueNext(); 333} 334 335void 336DMASequencer::recordRequestType(DMASequencerRequestType requestType) 337{ 338 DPRINTF(RubyStats, "Recorded statistic: %s\n", 339 DMASequencerRequestType_to_string(requestType)); 340} 341 342DMASequencer * 343DMASequencerParams::create() 344{ 345 return new DMASequencer(this); 346} 347