CacheRecorder.hh revision 12492
12381SN/A/* 210719SMarco.Balboni@ARM.com * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 38711SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc. 48711SN/A * All rights reserved. 58711SN/A * 68711SN/A * Redistribution and use in source and binary forms, with or without 78711SN/A * modification, are permitted provided that the following conditions are 88711SN/A * met: redistributions of source code must retain the above copyright 98711SN/A * notice, this list of conditions and the following disclaimer; 108711SN/A * redistributions in binary form must reproduce the above copyright 118711SN/A * notice, this list of conditions and the following disclaimer in the 128711SN/A * documentation and/or other materials provided with the distribution; 138711SN/A * neither the name of the copyright holders nor the names of its 142381SN/A * contributors may be used to endorse or promote products derived from 152381SN/A * this software without specific prior written permission. 162381SN/A * 172381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282381SN/A */ 292381SN/A 302381SN/A/* 312381SN/A * Recording cache requests made to a ruby cache at certain ruby 322381SN/A * time. Also dump the requests to a gziped file. 332381SN/A */ 342381SN/A 352381SN/A#ifndef __MEM_RUBY_SYSTEM_CACHERECORDER_HH__ 362381SN/A#define __MEM_RUBY_SYSTEM_CACHERECORDER_HH__ 372381SN/A 382381SN/A#include <vector> 392665SN/A 402665SN/A#include "base/types.hh" 412772SN/A#include "mem/protocol/RubyRequestType.hh" 428715SN/A#include "mem/ruby/common/Address.hh" 438922SN/A#include "mem/ruby/common/DataBlock.hh" 442381SN/A#include "mem/ruby/common/TypeDefines.hh" 452381SN/A 462381SN/Aclass Sequencer; 472982SN/A 4810405Sandreas.hansson@arm.com/*! 492381SN/A * Class for recording cache contents. Note that the last element of the 502381SN/A * class is an array of length zero. It is used for creating variable 5110405Sandreas.hansson@arm.com * length object, so that while writing the data to a file one does not 5210405Sandreas.hansson@arm.com * need to copy the meta data and the actual data separately. 532381SN/A */ 5410402SN/Aclass TraceRecord { 5510405Sandreas.hansson@arm.com public: 5610405Sandreas.hansson@arm.com int m_cntrl_id; 572381SN/A Tick m_time; 589036SN/A Addr m_data_address; 5910405Sandreas.hansson@arm.com Addr m_pc_address; 6010405Sandreas.hansson@arm.com RubyRequestType m_type; 6110405Sandreas.hansson@arm.com uint8_t m_data[0]; 6210405Sandreas.hansson@arm.com 639036SN/A void print(std::ostream& out) const; 6410405Sandreas.hansson@arm.com}; 6510405Sandreas.hansson@arm.com 6610405Sandreas.hansson@arm.comclass CacheRecorder 6710405Sandreas.hansson@arm.com{ 689036SN/A public: 6910405Sandreas.hansson@arm.com CacheRecorder(); 702381SN/A ~CacheRecorder(); 719031SN/A 729036SN/A CacheRecorder(uint8_t* uncompressed_trace, 739036SN/A uint64_t uncompressed_trace_size, 748922SN/A std::vector<Sequencer*>& SequencerMap, 7510405Sandreas.hansson@arm.com uint64_t block_size_bytes); 7610405Sandreas.hansson@arm.com void addRecord(int cntrl, Addr data_addr, Addr pc_addr, 779092SN/A RubyRequestType type, Tick time, DataBlock& data); 789715SN/A 799715SN/A uint64_t aggregateRecords(uint8_t **data, uint64_t size); 8010713Sandreas.hansson@arm.com 819092SN/A /*! 829092SN/A * Function for flushing the memory contents of the caches to the 8310405Sandreas.hansson@arm.com * main memory. It goes through the recorded contents of the caches, 8410405Sandreas.hansson@arm.com * and issues flush requests. Except for the first one, a flush request 8510405Sandreas.hansson@arm.com * is issued only after the previous one has completed. This currently 868922SN/A * requires use of MOESI Hammer protocol since only that protocol 8710405Sandreas.hansson@arm.com * supports flush requests. 882381SN/A */ 899036SN/A void enqueueNextFlushRequest(); 908922SN/A 919036SN/A /*! 9210405Sandreas.hansson@arm.com * Function for fetching warming up the memory and the caches. It goes 9310405Sandreas.hansson@arm.com * through the recorded contents of the caches, as available in the 942381SN/A * checkpoint and issues fetch requests. Except for the first one, a 952381SN/A * fetch request is issued only after the previous one has completed. 962381SN/A * It should be possible to use this with any protocol. 9710405Sandreas.hansson@arm.com */ 9810405Sandreas.hansson@arm.com void enqueueNextFetchRequest(); 9910405Sandreas.hansson@arm.com 1008922SN/A private: 1018922SN/A // Private copy constructor and assignment operator 1028922SN/A CacheRecorder(const CacheRecorder& obj); 1038922SN/A CacheRecorder& operator=(const CacheRecorder& obj); 1048948SN/A 10510405Sandreas.hansson@arm.com std::vector<TraceRecord*> m_records; 1068948SN/A uint8_t* m_uncompressed_trace; 1078975SN/A uint64_t m_uncompressed_trace_size; 10810405Sandreas.hansson@arm.com std::vector<Sequencer*> m_seq_map; 1098922SN/A uint64_t m_bytes_read; 1108948SN/A uint64_t m_records_read; 11110405Sandreas.hansson@arm.com uint64_t m_records_flushed; 1128948SN/A uint64_t m_block_size_bytes; 1138975SN/A}; 11410405Sandreas.hansson@arm.com 1158948SN/Ainline bool 1168948SN/AcompareTraceRecords(const TraceRecord* n1, const TraceRecord* n2) 11710405Sandreas.hansson@arm.com{ 1188948SN/A return n1->m_time > n2->m_time; 1198922SN/A} 12010405Sandreas.hansson@arm.com 1218922SN/Ainline std::ostream& 1228948SN/Aoperator<<(std::ostream& out, const TraceRecord& obj) 12310405Sandreas.hansson@arm.com{ 1248948SN/A obj.print(out); 1258922SN/A out << std::flush; 12610405Sandreas.hansson@arm.com return out; 1278922SN/A} 1288948SN/A 12910405Sandreas.hansson@arm.com#endif //__MEM_RUBY_SYSTEM_CACHERECORDER_HH__ 1308948SN/A