CacheRecorder.hh revision 10302
16145SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 38683SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc. 46145SN/A * All rights reserved. 56145SN/A * 66145SN/A * Redistribution and use in source and binary forms, with or without 76145SN/A * modification, are permitted provided that the following conditions are 86145SN/A * met: redistributions of source code must retain the above copyright 96145SN/A * notice, this list of conditions and the following disclaimer; 106145SN/A * redistributions in binary form must reproduce the above copyright 116145SN/A * notice, this list of conditions and the following disclaimer in the 126145SN/A * documentation and/or other materials provided with the distribution; 136145SN/A * neither the name of the copyright holders nor the names of its 146145SN/A * contributors may be used to endorse or promote products derived from 156145SN/A * this software without specific prior written permission. 166145SN/A * 176145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286145SN/A */ 296145SN/A 306145SN/A/* 317054SN/A * Recording cache requests made to a ruby cache at certain ruby 327054SN/A * time. Also dump the requests to a gziped file. 336145SN/A */ 346145SN/A 357054SN/A#ifndef __MEM_RUBY_RECORDER_CACHERECORDER_HH__ 367054SN/A#define __MEM_RUBY_RECORDER_CACHERECORDER_HH__ 376145SN/A 387456SN/A#include <vector> 397002SN/A 408683SN/A#include "base/hashmap.hh" 4110302Snilay@cs.wisc.edu#include "base/types.hh" 428165SN/A#include "mem/protocol/RubyRequestType.hh" 438683SN/A#include "mem/ruby/common/Address.hh" 448683SN/A#include "mem/ruby/common/DataBlock.hh" 458683SN/A#include "mem/ruby/common/TypeDefines.hh" 466145SN/A 476890SN/Aclass Sequencer; 486145SN/A 498683SN/A/*! 508683SN/A * Class for recording cache contents. Note that the last element of the 518683SN/A * class is an array of length zero. It is used for creating variable 528683SN/A * length object, so that while writing the data to a file one does not 538683SN/A * need to copy the meta data and the actual data separately. 548683SN/A */ 558683SN/Aclass TraceRecord { 568683SN/A public: 578683SN/A int m_cntrl_id; 5810302Snilay@cs.wisc.edu Tick m_time; 598683SN/A physical_address_t m_data_address; 608683SN/A physical_address_t m_pc_address; 618683SN/A RubyRequestType m_type; 628683SN/A uint8_t m_data[0]; 638683SN/A 648683SN/A void print(std::ostream& out) const; 658683SN/A}; 668683SN/A 677054SN/Aclass CacheRecorder 687054SN/A{ 697054SN/A public: 708683SN/A CacheRecorder(); 718683SN/A ~CacheRecorder(); 726145SN/A 738683SN/A CacheRecorder(uint8_t* uncompressed_trace, 748683SN/A uint64_t uncompressed_trace_size, 7510163SN/A std::vector<Sequencer*>& SequencerMap, 7610163SN/A uint64_t block_size_bytes); 778683SN/A void addRecord(int cntrl, const physical_address_t data_addr, 788683SN/A const physical_address_t pc_addr, RubyRequestType type, 7910302Snilay@cs.wisc.edu Tick time, DataBlock& data); 808683SN/A 818683SN/A uint64 aggregateRecords(uint8_t** data, uint64 size); 828683SN/A 838683SN/A /*! 848683SN/A * Function for flushing the memory contents of the caches to the 858683SN/A * main memory. It goes through the recorded contents of the caches, 868683SN/A * and issues flush requests. Except for the first one, a flush request 878683SN/A * is issued only after the previous one has completed. This currently 888683SN/A * requires use of MOESI Hammer protocol since only that protocol 898683SN/A * supports flush requests. 908683SN/A */ 918683SN/A void enqueueNextFlushRequest(); 928683SN/A 938683SN/A /*! 948683SN/A * Function for fetching warming up the memory and the caches. It goes 958683SN/A * through the recorded contents of the caches, as available in the 968683SN/A * checkpoint and issues fetch requests. Except for the first one, a 978683SN/A * fetch request is issued only after the previous one has completed. 988683SN/A * It should be possible to use this with any protocol. 998683SN/A */ 1008683SN/A void enqueueNextFetchRequest(); 1016145SN/A 1027054SN/A private: 1037054SN/A // Private copy constructor and assignment operator 1047054SN/A CacheRecorder(const CacheRecorder& obj); 1057054SN/A CacheRecorder& operator=(const CacheRecorder& obj); 1066145SN/A 1078683SN/A std::vector<TraceRecord*> m_records; 1088683SN/A uint8_t* m_uncompressed_trace; 1098683SN/A uint64_t m_uncompressed_trace_size; 1108683SN/A std::vector<Sequencer*> m_seq_map; 1118683SN/A uint64_t m_bytes_read; 1128683SN/A uint64_t m_records_read; 1138683SN/A uint64_t m_records_flushed; 11410163SN/A uint64_t m_block_size_bytes; 1156145SN/A}; 1166145SN/A 1178683SN/Ainline bool 1188683SN/AcompareTraceRecords(const TraceRecord* n1, const TraceRecord* n2) 1198683SN/A{ 1208683SN/A return n1->m_time > n2->m_time; 1218683SN/A} 1228683SN/A 1237054SN/Ainline std::ostream& 1248683SN/Aoperator<<(std::ostream& out, const TraceRecord& obj) 1256145SN/A{ 1267054SN/A obj.print(out); 1277054SN/A out << std::flush; 1287054SN/A return out; 1296145SN/A} 1306145SN/A 1317054SN/A#endif // __MEM_RUBY_RECORDER_CACHERECORDER_HH__ 132