CacheMemory.cc revision 10970:ea8bdb1d9f1e
111296Sandreas.sandberg@arm.com/* 211296Sandreas.sandberg@arm.com * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 311296Sandreas.sandberg@arm.com * All rights reserved. 411296Sandreas.sandberg@arm.com * 511296Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611296Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711296Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811296Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911296Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011296Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111296Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211296Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311296Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411296Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511296Sandreas.sandberg@arm.com * 1611296Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711296Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811296Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911296Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011296Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111296Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211296Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311296Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411296Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511296Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611296Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711296Sandreas.sandberg@arm.com */ 2811296Sandreas.sandberg@arm.com 2911296Sandreas.sandberg@arm.com#include "base/intmath.hh" 3011296Sandreas.sandberg@arm.com#include "debug/RubyCache.hh" 3111296Sandreas.sandberg@arm.com#include "debug/RubyCacheTrace.hh" 3211296Sandreas.sandberg@arm.com#include "debug/RubyResourceStalls.hh" 3311296Sandreas.sandberg@arm.com#include "debug/RubyStats.hh" 3411296Sandreas.sandberg@arm.com#include "mem/protocol/AccessPermission.hh" 3511296Sandreas.sandberg@arm.com#include "mem/ruby/structures/CacheMemory.hh" 3611296Sandreas.sandberg@arm.com#include "mem/ruby/system/System.hh" 3711296Sandreas.sandberg@arm.com 3811296Sandreas.sandberg@arm.comusing namespace std; 3911296Sandreas.sandberg@arm.com 4011296Sandreas.sandberg@arm.comostream& 4111296Sandreas.sandberg@arm.comoperator<<(ostream& out, const CacheMemory& obj) 4211296Sandreas.sandberg@arm.com{ 4311296Sandreas.sandberg@arm.com obj.print(out); 4411296Sandreas.sandberg@arm.com out << flush; 4511296Sandreas.sandberg@arm.com return out; 4611296Sandreas.sandberg@arm.com} 4711296Sandreas.sandberg@arm.com 4811296Sandreas.sandberg@arm.comCacheMemory * 4911296Sandreas.sandberg@arm.comRubyCacheParams::create() 5011296Sandreas.sandberg@arm.com{ 5111296Sandreas.sandberg@arm.com return new CacheMemory(this); 5211296Sandreas.sandberg@arm.com} 5311296Sandreas.sandberg@arm.com 5411296Sandreas.sandberg@arm.comCacheMemory::CacheMemory(const Params *p) 5511296Sandreas.sandberg@arm.com : SimObject(p), 5611296Sandreas.sandberg@arm.com dataArray(p->dataArrayBanks, p->dataAccessLatency, 5711296Sandreas.sandberg@arm.com p->start_index_bit, p->ruby_system), 5811296Sandreas.sandberg@arm.com tagArray(p->tagArrayBanks, p->tagAccessLatency, 5911296Sandreas.sandberg@arm.com p->start_index_bit, p->ruby_system) 6011296Sandreas.sandberg@arm.com{ 6111296Sandreas.sandberg@arm.com m_cache_size = p->size; 6211296Sandreas.sandberg@arm.com m_latency = p->latency; 6311296Sandreas.sandberg@arm.com m_cache_assoc = p->assoc; 6411296Sandreas.sandberg@arm.com m_replacementPolicy_ptr = p->replacement_policy; 6511296Sandreas.sandberg@arm.com m_start_index_bit = p->start_index_bit; 6611296Sandreas.sandberg@arm.com m_is_instruction_only_cache = p->is_icache; 67 m_resource_stalls = p->resourceStalls; 68} 69 70void 71CacheMemory::init() 72{ 73 m_cache_num_sets = (m_cache_size / m_cache_assoc) / 74 RubySystem::getBlockSizeBytes(); 75 assert(m_cache_num_sets > 1); 76 m_cache_num_set_bits = floorLog2(m_cache_num_sets); 77 assert(m_cache_num_set_bits > 0); 78 79 m_cache.resize(m_cache_num_sets); 80 for (int i = 0; i < m_cache_num_sets; i++) { 81 m_cache[i].resize(m_cache_assoc); 82 for (int j = 0; j < m_cache_assoc; j++) { 83 m_cache[i][j] = NULL; 84 } 85 } 86} 87 88CacheMemory::~CacheMemory() 89{ 90 if (m_replacementPolicy_ptr != NULL) 91 delete m_replacementPolicy_ptr; 92 for (int i = 0; i < m_cache_num_sets; i++) { 93 for (int j = 0; j < m_cache_assoc; j++) { 94 delete m_cache[i][j]; 95 } 96 } 97} 98 99// convert a Address to its location in the cache 100int64 101CacheMemory::addressToCacheSet(const Address& address) const 102{ 103 assert(address == line_address(address)); 104 return address.bitSelect(m_start_index_bit, 105 m_start_index_bit + m_cache_num_set_bits - 1); 106} 107 108// Given a cache index: returns the index of the tag in a set. 109// returns -1 if the tag is not found. 110int 111CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const 112{ 113 assert(tag == line_address(tag)); 114 // search the set for the tags 115 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); 116 if (it != m_tag_index.end()) 117 if (m_cache[cacheSet][it->second]->m_Permission != 118 AccessPermission_NotPresent) 119 return it->second; 120 return -1; // Not found 121} 122 123// Given a cache index: returns the index of the tag in a set. 124// returns -1 if the tag is not found. 125int 126CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, 127 const Address& tag) const 128{ 129 assert(tag == line_address(tag)); 130 // search the set for the tags 131 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); 132 if (it != m_tag_index.end()) 133 return it->second; 134 return -1; // Not found 135} 136 137bool 138CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, 139 DataBlock*& data_ptr) 140{ 141 assert(address == line_address(address)); 142 DPRINTF(RubyCache, "address: %s\n", address); 143 int64 cacheSet = addressToCacheSet(address); 144 int loc = findTagInSet(cacheSet, address); 145 if (loc != -1) { 146 // Do we even have a tag match? 147 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 148 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 149 data_ptr = &(entry->getDataBlk()); 150 151 if (entry->m_Permission == AccessPermission_Read_Write) { 152 return true; 153 } 154 if ((entry->m_Permission == AccessPermission_Read_Only) && 155 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { 156 return true; 157 } 158 // The line must not be accessible 159 } 160 data_ptr = NULL; 161 return false; 162} 163 164bool 165CacheMemory::testCacheAccess(const Address& address, RubyRequestType type, 166 DataBlock*& data_ptr) 167{ 168 assert(address == line_address(address)); 169 DPRINTF(RubyCache, "address: %s\n", address); 170 int64 cacheSet = addressToCacheSet(address); 171 int loc = findTagInSet(cacheSet, address); 172 173 if (loc != -1) { 174 // Do we even have a tag match? 175 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 176 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 177 data_ptr = &(entry->getDataBlk()); 178 179 return m_cache[cacheSet][loc]->m_Permission != 180 AccessPermission_NotPresent; 181 } 182 183 data_ptr = NULL; 184 return false; 185} 186 187// tests to see if an address is present in the cache 188bool 189CacheMemory::isTagPresent(const Address& address) const 190{ 191 assert(address == line_address(address)); 192 int64 cacheSet = addressToCacheSet(address); 193 int loc = findTagInSet(cacheSet, address); 194 195 if (loc == -1) { 196 // We didn't find the tag 197 DPRINTF(RubyCache, "No tag match for address: %s\n", address); 198 return false; 199 } 200 DPRINTF(RubyCache, "address: %s found\n", address); 201 return true; 202} 203 204// Returns true if there is: 205// a) a tag match on this address or there is 206// b) an unused line in the same cache "way" 207bool 208CacheMemory::cacheAvail(const Address& address) const 209{ 210 assert(address == line_address(address)); 211 212 int64 cacheSet = addressToCacheSet(address); 213 214 for (int i = 0; i < m_cache_assoc; i++) { 215 AbstractCacheEntry* entry = m_cache[cacheSet][i]; 216 if (entry != NULL) { 217 if (entry->m_Address == address || 218 entry->m_Permission == AccessPermission_NotPresent) { 219 // Already in the cache or we found an empty entry 220 return true; 221 } 222 } else { 223 return true; 224 } 225 } 226 return false; 227} 228 229AbstractCacheEntry* 230CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry) 231{ 232 assert(address == line_address(address)); 233 assert(!isTagPresent(address)); 234 assert(cacheAvail(address)); 235 DPRINTF(RubyCache, "address: %s\n", address); 236 237 // Find the first open slot 238 int64 cacheSet = addressToCacheSet(address); 239 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; 240 for (int i = 0; i < m_cache_assoc; i++) { 241 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { 242 set[i] = entry; // Init entry 243 set[i]->m_Address = address; 244 set[i]->m_Permission = AccessPermission_Invalid; 245 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n", 246 address); 247 set[i]->m_locked = -1; 248 m_tag_index[address] = i; 249 250 m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 251 252 return entry; 253 } 254 } 255 panic("Allocate didn't find an available entry"); 256} 257 258void 259CacheMemory::deallocate(const Address& address) 260{ 261 assert(address == line_address(address)); 262 assert(isTagPresent(address)); 263 DPRINTF(RubyCache, "address: %s\n", address); 264 int64 cacheSet = addressToCacheSet(address); 265 int loc = findTagInSet(cacheSet, address); 266 if (loc != -1) { 267 delete m_cache[cacheSet][loc]; 268 m_cache[cacheSet][loc] = NULL; 269 m_tag_index.erase(address); 270 } 271} 272 273// Returns with the physical address of the conflicting cache line 274Address 275CacheMemory::cacheProbe(const Address& address) const 276{ 277 assert(address == line_address(address)); 278 assert(!cacheAvail(address)); 279 280 int64 cacheSet = addressToCacheSet(address); 281 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> 282 m_Address; 283} 284 285// looks an address up in the cache 286AbstractCacheEntry* 287CacheMemory::lookup(const Address& address) 288{ 289 assert(address == line_address(address)); 290 int64 cacheSet = addressToCacheSet(address); 291 int loc = findTagInSet(cacheSet, address); 292 if(loc == -1) return NULL; 293 return m_cache[cacheSet][loc]; 294} 295 296// looks an address up in the cache 297const AbstractCacheEntry* 298CacheMemory::lookup(const Address& address) const 299{ 300 assert(address == line_address(address)); 301 int64 cacheSet = addressToCacheSet(address); 302 int loc = findTagInSet(cacheSet, address); 303 if(loc == -1) return NULL; 304 return m_cache[cacheSet][loc]; 305} 306 307// Sets the most recently used bit for a cache block 308void 309CacheMemory::setMRU(const Address& address) 310{ 311 int64 cacheSet = addressToCacheSet(address); 312 int loc = findTagInSet(cacheSet, address); 313 314 if(loc != -1) 315 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 316} 317 318void 319CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 320{ 321 uint64 warmedUpBlocks = 0; 322 uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets 323 * (uint64)m_cache_assoc; 324 325 for (int i = 0; i < m_cache_num_sets; i++) { 326 for (int j = 0; j < m_cache_assoc; j++) { 327 if (m_cache[i][j] != NULL) { 328 AccessPermission perm = m_cache[i][j]->m_Permission; 329 RubyRequestType request_type = RubyRequestType_NULL; 330 if (perm == AccessPermission_Read_Only) { 331 if (m_is_instruction_only_cache) { 332 request_type = RubyRequestType_IFETCH; 333 } else { 334 request_type = RubyRequestType_LD; 335 } 336 } else if (perm == AccessPermission_Read_Write) { 337 request_type = RubyRequestType_ST; 338 } 339 340 if (request_type != RubyRequestType_NULL) { 341 tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(), 342 0, request_type, 343 m_replacementPolicy_ptr->getLastAccess(i, j), 344 m_cache[i][j]->getDataBlk()); 345 warmedUpBlocks++; 346 } 347 } 348 } 349 } 350 351 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" 352 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, 353 (uint64)m_cache_num_sets * (uint64)m_cache_assoc, 354 (float(warmedUpBlocks)/float(totalBlocks))*100.0); 355} 356 357void 358CacheMemory::print(ostream& out) const 359{ 360 out << "Cache dump: " << name() << endl; 361 for (int i = 0; i < m_cache_num_sets; i++) { 362 for (int j = 0; j < m_cache_assoc; j++) { 363 if (m_cache[i][j] != NULL) { 364 out << " Index: " << i 365 << " way: " << j 366 << " entry: " << *m_cache[i][j] << endl; 367 } else { 368 out << " Index: " << i 369 << " way: " << j 370 << " entry: NULL" << endl; 371 } 372 } 373 } 374} 375 376void 377CacheMemory::printData(ostream& out) const 378{ 379 out << "printData() not supported" << endl; 380} 381 382void 383CacheMemory::setLocked(const Address& address, int context) 384{ 385 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); 386 assert(address == line_address(address)); 387 int64 cacheSet = addressToCacheSet(address); 388 int loc = findTagInSet(cacheSet, address); 389 assert(loc != -1); 390 m_cache[cacheSet][loc]->m_locked = context; 391} 392 393void 394CacheMemory::clearLocked(const Address& address) 395{ 396 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); 397 assert(address == line_address(address)); 398 int64 cacheSet = addressToCacheSet(address); 399 int loc = findTagInSet(cacheSet, address); 400 assert(loc != -1); 401 m_cache[cacheSet][loc]->m_locked = -1; 402} 403 404bool 405CacheMemory::isLocked(const Address& address, int context) 406{ 407 assert(address == line_address(address)); 408 int64 cacheSet = addressToCacheSet(address); 409 int loc = findTagInSet(cacheSet, address); 410 assert(loc != -1); 411 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", 412 address, m_cache[cacheSet][loc]->m_locked, context); 413 return m_cache[cacheSet][loc]->m_locked == context; 414} 415 416void 417CacheMemory::regStats() 418{ 419 m_demand_hits 420 .name(name() + ".demand_hits") 421 .desc("Number of cache demand hits") 422 ; 423 424 m_demand_misses 425 .name(name() + ".demand_misses") 426 .desc("Number of cache demand misses") 427 ; 428 429 m_demand_accesses 430 .name(name() + ".demand_accesses") 431 .desc("Number of cache demand accesses") 432 ; 433 434 m_demand_accesses = m_demand_hits + m_demand_misses; 435 436 m_sw_prefetches 437 .name(name() + ".total_sw_prefetches") 438 .desc("Number of software prefetches") 439 .flags(Stats::nozero) 440 ; 441 442 m_hw_prefetches 443 .name(name() + ".total_hw_prefetches") 444 .desc("Number of hardware prefetches") 445 .flags(Stats::nozero) 446 ; 447 448 m_prefetches 449 .name(name() + ".total_prefetches") 450 .desc("Number of prefetches") 451 .flags(Stats::nozero) 452 ; 453 454 m_prefetches = m_sw_prefetches + m_hw_prefetches; 455 456 m_accessModeType 457 .init(RubyRequestType_NUM) 458 .name(name() + ".access_mode") 459 .flags(Stats::pdf | Stats::total) 460 ; 461 for (int i = 0; i < RubyAccessMode_NUM; i++) { 462 m_accessModeType 463 .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) 464 .flags(Stats::nozero) 465 ; 466 } 467 468 numDataArrayReads 469 .name(name() + ".num_data_array_reads") 470 .desc("number of data array reads") 471 .flags(Stats::nozero) 472 ; 473 474 numDataArrayWrites 475 .name(name() + ".num_data_array_writes") 476 .desc("number of data array writes") 477 .flags(Stats::nozero) 478 ; 479 480 numTagArrayReads 481 .name(name() + ".num_tag_array_reads") 482 .desc("number of tag array reads") 483 .flags(Stats::nozero) 484 ; 485 486 numTagArrayWrites 487 .name(name() + ".num_tag_array_writes") 488 .desc("number of tag array writes") 489 .flags(Stats::nozero) 490 ; 491 492 numTagArrayStalls 493 .name(name() + ".num_tag_array_stalls") 494 .desc("number of stalls caused by tag array") 495 .flags(Stats::nozero) 496 ; 497 498 numDataArrayStalls 499 .name(name() + ".num_data_array_stalls") 500 .desc("number of stalls caused by data array") 501 .flags(Stats::nozero) 502 ; 503} 504 505void 506CacheMemory::recordRequestType(CacheRequestType requestType) 507{ 508 DPRINTF(RubyStats, "Recorded statistic: %s\n", 509 CacheRequestType_to_string(requestType)); 510 switch(requestType) { 511 case CacheRequestType_DataArrayRead: 512 numDataArrayReads++; 513 return; 514 case CacheRequestType_DataArrayWrite: 515 numDataArrayWrites++; 516 return; 517 case CacheRequestType_TagArrayRead: 518 numTagArrayReads++; 519 return; 520 case CacheRequestType_TagArrayWrite: 521 numTagArrayWrites++; 522 return; 523 default: 524 warn("CacheMemory access_type not found: %s", 525 CacheRequestType_to_string(requestType)); 526 } 527} 528 529bool 530CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) 531{ 532 if (!m_resource_stalls) { 533 return true; 534 } 535 536 if (res == CacheResourceType_TagArray) { 537 if (tagArray.tryAccess(addressToCacheSet(addr))) return true; 538 else { 539 DPRINTF(RubyResourceStalls, 540 "Tag array stall on addr %s in set %d\n", 541 addr, addressToCacheSet(addr)); 542 numTagArrayStalls++; 543 return false; 544 } 545 } else if (res == CacheResourceType_DataArray) { 546 if (dataArray.tryAccess(addressToCacheSet(addr))) return true; 547 else { 548 DPRINTF(RubyResourceStalls, 549 "Data array stall on addr %s in set %d\n", 550 addr, addressToCacheSet(addr)); 551 numDataArrayStalls++; 552 return false; 553 } 554 } else { 555 assert(false); 556 return true; 557 } 558} 559