CacheMemory.cc revision 11308
16782SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310973Sdavid.hashe@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 46782SN/A * All rights reserved. 56782SN/A * 66782SN/A * Redistribution and use in source and binary forms, with or without 76782SN/A * modification, are permitted provided that the following conditions are 86782SN/A * met: redistributions of source code must retain the above copyright 96782SN/A * notice, this list of conditions and the following disclaimer; 106782SN/A * redistributions in binary form must reproduce the above copyright 116782SN/A * notice, this list of conditions and the following disclaimer in the 126782SN/A * documentation and/or other materials provided with the distribution; 136782SN/A * neither the name of the copyright holders nor the names of its 146782SN/A * contributors may be used to endorse or promote products derived from 156782SN/A * this software without specific prior written permission. 166782SN/A * 176782SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186782SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196782SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206782SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216782SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226782SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236782SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246782SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256782SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266782SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276782SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286782SN/A */ 296782SN/A 307056SN/A#include "base/intmath.hh" 318232SN/A#include "debug/RubyCache.hh" 328937SN/A#include "debug/RubyCacheTrace.hh" 339105SN/A#include "debug/RubyResourceStalls.hh" 349104SN/A#include "debug/RubyStats.hh" 358683SN/A#include "mem/protocol/AccessPermission.hh" 3610301Snilay@cs.wisc.edu#include "mem/ruby/structures/CacheMemory.hh" 3711108Sdavid.hashe@amd.com#include "mem/ruby/system/RubySystem.hh" 3811308Santhony.gutierrez@amd.com#include "mem/ruby/system/WeightedLRUPolicy.hh" 396782SN/A 407055SN/Ausing namespace std; 417055SN/A 427039SN/Aostream& 437039SN/Aoperator<<(ostream& out, const CacheMemory& obj) 446782SN/A{ 457039SN/A obj.print(out); 467039SN/A out << flush; 477039SN/A return out; 486782SN/A} 496782SN/A 506876SN/ACacheMemory * 516876SN/ARubyCacheParams::create() 526782SN/A{ 536876SN/A return new CacheMemory(this); 546782SN/A} 556782SN/A 566876SN/ACacheMemory::CacheMemory(const Params *p) 579105SN/A : SimObject(p), 5810919Sbrandon.potter@amd.com dataArray(p->dataArrayBanks, p->dataAccessLatency, 5910919Sbrandon.potter@amd.com p->start_index_bit, p->ruby_system), 6010919Sbrandon.potter@amd.com tagArray(p->tagArrayBanks, p->tagAccessLatency, 6110919Sbrandon.potter@amd.com p->start_index_bit, p->ruby_system) 626782SN/A{ 636882SN/A m_cache_size = p->size; 646876SN/A m_cache_assoc = p->assoc; 6510970Sdavid.hashe@amd.com m_replacementPolicy_ptr = p->replacement_policy; 6610980Sdavid.hashe@amd.com m_replacementPolicy_ptr->setCache(this); 677564SN/A m_start_index_bit = p->start_index_bit; 688653SN/A m_is_instruction_only_cache = p->is_icache; 699105SN/A m_resource_stalls = p->resourceStalls; 7011308Santhony.gutierrez@amd.com m_block_size = p->block_size; // may be 0 at this point. Updated in init() 716876SN/A} 726876SN/A 737039SN/Avoid 747039SN/ACacheMemory::init() 756876SN/A{ 7611308Santhony.gutierrez@amd.com if (m_block_size == 0) { 7711308Santhony.gutierrez@amd.com m_block_size = RubySystem::getBlockSizeBytes(); 7811308Santhony.gutierrez@amd.com } 7911308Santhony.gutierrez@amd.com m_cache_num_sets = (m_cache_size / m_cache_assoc) / m_block_size; 806882SN/A assert(m_cache_num_sets > 1); 817056SN/A m_cache_num_set_bits = floorLog2(m_cache_num_sets); 826882SN/A assert(m_cache_num_set_bits > 0); 837039SN/A 8411308Santhony.gutierrez@amd.com m_cache.resize(m_cache_num_sets, 8511308Santhony.gutierrez@amd.com std::vector<AbstractCacheEntry*>(m_cache_assoc, nullptr)); 866782SN/A} 876782SN/A 886782SN/ACacheMemory::~CacheMemory() 896782SN/A{ 9011308Santhony.gutierrez@amd.com if (m_replacementPolicy_ptr) 917039SN/A delete m_replacementPolicy_ptr; 927039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 937039SN/A for (int j = 0; j < m_cache_assoc; j++) { 947039SN/A delete m_cache[i][j]; 957039SN/A } 966783SN/A } 976782SN/A} 986782SN/A 996782SN/A// convert a Address to its location in the cache 10011061Snilay@cs.wisc.eduint64_t 10111025Snilay@cs.wisc.eduCacheMemory::addressToCacheSet(Addr address) const 1026782SN/A{ 10311025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 10411025Snilay@cs.wisc.edu return bitSelect(address, m_start_index_bit, 10511025Snilay@cs.wisc.edu m_start_index_bit + m_cache_num_set_bits - 1); 1066782SN/A} 1076782SN/A 1086782SN/A// Given a cache index: returns the index of the tag in a set. 1096782SN/A// returns -1 if the tag is not found. 1107039SN/Aint 11111061Snilay@cs.wisc.eduCacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const 1126782SN/A{ 11311025Snilay@cs.wisc.edu assert(tag == makeLineAddress(tag)); 1147039SN/A // search the set for the tags 11511168Sandreas.hansson@arm.com auto it = m_tag_index.find(tag); 1167039SN/A if (it != m_tag_index.end()) 1177039SN/A if (m_cache[cacheSet][it->second]->m_Permission != 1187039SN/A AccessPermission_NotPresent) 1197039SN/A return it->second; 1207039SN/A return -1; // Not found 1216782SN/A} 1226782SN/A 1236782SN/A// Given a cache index: returns the index of the tag in a set. 1246782SN/A// returns -1 if the tag is not found. 1257039SN/Aint 12611061Snilay@cs.wisc.eduCacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, 12711025Snilay@cs.wisc.edu Addr tag) const 1286782SN/A{ 12911025Snilay@cs.wisc.edu assert(tag == makeLineAddress(tag)); 1307039SN/A // search the set for the tags 13111168Sandreas.hansson@arm.com auto it = m_tag_index.find(tag); 1327039SN/A if (it != m_tag_index.end()) 1337039SN/A return it->second; 1347039SN/A return -1; // Not found 1356782SN/A} 1366782SN/A 13710973Sdavid.hashe@amd.com// Given an unique cache block identifier (idx): return the valid address 13810973Sdavid.hashe@amd.com// stored by the cache block. If the block is invalid/notpresent, the 13910973Sdavid.hashe@amd.com// function returns the 0 address 14011025Snilay@cs.wisc.eduAddr 14110973Sdavid.hashe@amd.comCacheMemory::getAddressAtIdx(int idx) const 14210973Sdavid.hashe@amd.com{ 14311025Snilay@cs.wisc.edu Addr tmp(0); 14410973Sdavid.hashe@amd.com 14510973Sdavid.hashe@amd.com int set = idx / m_cache_assoc; 14610973Sdavid.hashe@amd.com assert(set < m_cache_num_sets); 14710973Sdavid.hashe@amd.com 14810973Sdavid.hashe@amd.com int way = idx - set * m_cache_assoc; 14910973Sdavid.hashe@amd.com assert (way < m_cache_assoc); 15010973Sdavid.hashe@amd.com 15110973Sdavid.hashe@amd.com AbstractCacheEntry* entry = m_cache[set][way]; 15210973Sdavid.hashe@amd.com if (entry == NULL || 15310973Sdavid.hashe@amd.com entry->m_Permission == AccessPermission_Invalid || 15410973Sdavid.hashe@amd.com entry->m_Permission == AccessPermission_NotPresent) { 15510973Sdavid.hashe@amd.com return tmp; 15610973Sdavid.hashe@amd.com } 15710973Sdavid.hashe@amd.com return entry->m_Address; 15810973Sdavid.hashe@amd.com} 15910973Sdavid.hashe@amd.com 16011049Snilay@cs.wisc.edubool 16111049Snilay@cs.wisc.eduCacheMemory::tryCacheAccess(Addr address, RubyRequestType type, 16211049Snilay@cs.wisc.edu DataBlock*& data_ptr) 16311049Snilay@cs.wisc.edu{ 16411049Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 16511118Snilay@cs.wisc.edu DPRINTF(RubyCache, "address: %#x\n", address); 16611061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 16711049Snilay@cs.wisc.edu int loc = findTagInSet(cacheSet, address); 16811049Snilay@cs.wisc.edu if (loc != -1) { 16911049Snilay@cs.wisc.edu // Do we even have a tag match? 17011049Snilay@cs.wisc.edu AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 17111049Snilay@cs.wisc.edu m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 17211049Snilay@cs.wisc.edu data_ptr = &(entry->getDataBlk()); 17311049Snilay@cs.wisc.edu 17411049Snilay@cs.wisc.edu if (entry->m_Permission == AccessPermission_Read_Write) { 17511049Snilay@cs.wisc.edu return true; 17611049Snilay@cs.wisc.edu } 17711049Snilay@cs.wisc.edu if ((entry->m_Permission == AccessPermission_Read_Only) && 17811049Snilay@cs.wisc.edu (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { 17911049Snilay@cs.wisc.edu return true; 18011049Snilay@cs.wisc.edu } 18111049Snilay@cs.wisc.edu // The line must not be accessible 18211049Snilay@cs.wisc.edu } 18311049Snilay@cs.wisc.edu data_ptr = NULL; 18411049Snilay@cs.wisc.edu return false; 18511049Snilay@cs.wisc.edu} 18611049Snilay@cs.wisc.edu 18711049Snilay@cs.wisc.edubool 18811049Snilay@cs.wisc.eduCacheMemory::testCacheAccess(Addr address, RubyRequestType type, 18911049Snilay@cs.wisc.edu DataBlock*& data_ptr) 19011049Snilay@cs.wisc.edu{ 19111049Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 19211118Snilay@cs.wisc.edu DPRINTF(RubyCache, "address: %#x\n", address); 19311061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 19411049Snilay@cs.wisc.edu int loc = findTagInSet(cacheSet, address); 19511049Snilay@cs.wisc.edu 19611049Snilay@cs.wisc.edu if (loc != -1) { 19711049Snilay@cs.wisc.edu // Do we even have a tag match? 19811049Snilay@cs.wisc.edu AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 19911049Snilay@cs.wisc.edu m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 20011049Snilay@cs.wisc.edu data_ptr = &(entry->getDataBlk()); 20111049Snilay@cs.wisc.edu 20211049Snilay@cs.wisc.edu return m_cache[cacheSet][loc]->m_Permission != 20311049Snilay@cs.wisc.edu AccessPermission_NotPresent; 20411049Snilay@cs.wisc.edu } 20511049Snilay@cs.wisc.edu 20611049Snilay@cs.wisc.edu data_ptr = NULL; 20711049Snilay@cs.wisc.edu return false; 20811049Snilay@cs.wisc.edu} 20911049Snilay@cs.wisc.edu 2106782SN/A// tests to see if an address is present in the cache 2117039SN/Abool 21211025Snilay@cs.wisc.eduCacheMemory::isTagPresent(Addr address) const 2136782SN/A{ 21411025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 21511061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 2167039SN/A int loc = findTagInSet(cacheSet, address); 2176782SN/A 2187039SN/A if (loc == -1) { 2197039SN/A // We didn't find the tag 22011118Snilay@cs.wisc.edu DPRINTF(RubyCache, "No tag match for address: %#x\n", address); 2217039SN/A return false; 2227039SN/A } 22311118Snilay@cs.wisc.edu DPRINTF(RubyCache, "address: %#x found\n", address); 2247039SN/A return true; 2256782SN/A} 2266782SN/A 2276782SN/A// Returns true if there is: 2286782SN/A// a) a tag match on this address or there is 2296782SN/A// b) an unused line in the same cache "way" 2307039SN/Abool 23111025Snilay@cs.wisc.eduCacheMemory::cacheAvail(Addr address) const 2326782SN/A{ 23311025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 2346782SN/A 23511061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 2366782SN/A 2377039SN/A for (int i = 0; i < m_cache_assoc; i++) { 2387039SN/A AbstractCacheEntry* entry = m_cache[cacheSet][i]; 2397039SN/A if (entry != NULL) { 2407039SN/A if (entry->m_Address == address || 2417039SN/A entry->m_Permission == AccessPermission_NotPresent) { 2427039SN/A // Already in the cache or we found an empty entry 2437039SN/A return true; 2447039SN/A } 2457039SN/A } else { 2467039SN/A return true; 2477039SN/A } 2486782SN/A } 2497039SN/A return false; 2506782SN/A} 2516782SN/A 2527839SN/AAbstractCacheEntry* 25311086Snilay@cs.wisc.eduCacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch) 2546782SN/A{ 25511025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 2567039SN/A assert(!isTagPresent(address)); 2577039SN/A assert(cacheAvail(address)); 25811118Snilay@cs.wisc.edu DPRINTF(RubyCache, "address: %#x\n", address); 2596782SN/A 2607039SN/A // Find the first open slot 26111061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 2627454SN/A std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; 2637039SN/A for (int i = 0; i < m_cache_assoc; i++) { 2647039SN/A if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { 26511145Sjthestness@gmail.com if (set[i] && (set[i] != entry)) { 26611145Sjthestness@gmail.com warn_once("This protocol contains a cache entry handling bug: " 26711145Sjthestness@gmail.com "Entries in the cache should never be NotPresent! If\n" 26811145Sjthestness@gmail.com "this entry (%#x) is not tracked elsewhere, it will memory " 26911145Sjthestness@gmail.com "leak here. Fix your protocol to eliminate these!", 27011145Sjthestness@gmail.com address); 27111145Sjthestness@gmail.com } 2727039SN/A set[i] = entry; // Init entry 2737039SN/A set[i]->m_Address = address; 2747039SN/A set[i]->m_Permission = AccessPermission_Invalid; 2757039SN/A DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n", 2767039SN/A address); 2777839SN/A set[i]->m_locked = -1; 2787039SN/A m_tag_index[address] = i; 27911086Snilay@cs.wisc.edu entry->setSetIndex(cacheSet); 28011086Snilay@cs.wisc.edu entry->setWayIndex(i); 2816782SN/A 28210974Sdavid.hashe@amd.com if (touch) { 28310974Sdavid.hashe@amd.com m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 28410974Sdavid.hashe@amd.com } 2856782SN/A 2867839SN/A return entry; 2877039SN/A } 2886782SN/A } 2897805SN/A panic("Allocate didn't find an available entry"); 2906782SN/A} 2916782SN/A 2927039SN/Avoid 29311025Snilay@cs.wisc.eduCacheMemory::deallocate(Addr address) 2946782SN/A{ 29511025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 2967039SN/A assert(isTagPresent(address)); 29711118Snilay@cs.wisc.edu DPRINTF(RubyCache, "address: %#x\n", address); 29811061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 2997039SN/A int loc = findTagInSet(cacheSet, address); 3007039SN/A if (loc != -1) { 3017039SN/A delete m_cache[cacheSet][loc]; 3027039SN/A m_cache[cacheSet][loc] = NULL; 3037039SN/A m_tag_index.erase(address); 3047039SN/A } 3056782SN/A} 3066782SN/A 3076782SN/A// Returns with the physical address of the conflicting cache line 30811025Snilay@cs.wisc.eduAddr 30911025Snilay@cs.wisc.eduCacheMemory::cacheProbe(Addr address) const 3106782SN/A{ 31111025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 3127039SN/A assert(!cacheAvail(address)); 3136782SN/A 31411061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 3157039SN/A return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> 3167039SN/A m_Address; 3176782SN/A} 3186782SN/A 3196782SN/A// looks an address up in the cache 3207839SN/AAbstractCacheEntry* 32111025Snilay@cs.wisc.eduCacheMemory::lookup(Addr address) 3226782SN/A{ 32311025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 32411061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 3257039SN/A int loc = findTagInSet(cacheSet, address); 3267839SN/A if(loc == -1) return NULL; 3277839SN/A return m_cache[cacheSet][loc]; 3286782SN/A} 3296782SN/A 3306782SN/A// looks an address up in the cache 3317839SN/Aconst AbstractCacheEntry* 33211025Snilay@cs.wisc.eduCacheMemory::lookup(Addr address) const 3336782SN/A{ 33411025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 33511061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 3367039SN/A int loc = findTagInSet(cacheSet, address); 3377839SN/A if(loc == -1) return NULL; 3387839SN/A return m_cache[cacheSet][loc]; 3396782SN/A} 3406782SN/A 3416782SN/A// Sets the most recently used bit for a cache block 3427039SN/Avoid 34311025Snilay@cs.wisc.eduCacheMemory::setMRU(Addr address) 3446782SN/A{ 34511061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 3468828SN/A int loc = findTagInSet(cacheSet, address); 3476782SN/A 3488828SN/A if(loc != -1) 3499171SN/A m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 3506782SN/A} 3516782SN/A 3527039SN/Avoid 35311087Snilay@cs.wisc.eduCacheMemory::setMRU(const AbstractCacheEntry *e) 35411087Snilay@cs.wisc.edu{ 35511087Snilay@cs.wisc.edu uint32_t cacheSet = e->getSetIndex(); 35611087Snilay@cs.wisc.edu uint32_t loc = e->getWayIndex(); 35711087Snilay@cs.wisc.edu m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 35811087Snilay@cs.wisc.edu} 35911087Snilay@cs.wisc.edu 36011087Snilay@cs.wisc.eduvoid 36111308Santhony.gutierrez@amd.comCacheMemory::setMRU(Addr address, int occupancy) 36211308Santhony.gutierrez@amd.com{ 36311308Santhony.gutierrez@amd.com int64_t cacheSet = addressToCacheSet(address); 36411308Santhony.gutierrez@amd.com int loc = findTagInSet(cacheSet, address); 36511308Santhony.gutierrez@amd.com 36611308Santhony.gutierrez@amd.com if(loc != -1) { 36711308Santhony.gutierrez@amd.com if (m_replacementPolicy_ptr->useOccupancy()) { 36811308Santhony.gutierrez@amd.com (static_cast<WeightedLRUPolicy*>(m_replacementPolicy_ptr))-> 36911308Santhony.gutierrez@amd.com touch(cacheSet, loc, curTick(), occupancy); 37011308Santhony.gutierrez@amd.com } else { 37111308Santhony.gutierrez@amd.com m_replacementPolicy_ptr-> 37211308Santhony.gutierrez@amd.com touch(cacheSet, loc, curTick()); 37311308Santhony.gutierrez@amd.com } 37411308Santhony.gutierrez@amd.com } 37511308Santhony.gutierrez@amd.com} 37611308Santhony.gutierrez@amd.com 37711308Santhony.gutierrez@amd.comint 37811308Santhony.gutierrez@amd.comCacheMemory::getReplacementWeight(int64_t set, int64_t loc) 37911308Santhony.gutierrez@amd.com{ 38011308Santhony.gutierrez@amd.com assert(set < m_cache_num_sets); 38111308Santhony.gutierrez@amd.com assert(loc < m_cache_assoc); 38211308Santhony.gutierrez@amd.com int ret = 0; 38311308Santhony.gutierrez@amd.com if(m_cache[set][loc] != NULL) { 38411308Santhony.gutierrez@amd.com ret = m_cache[set][loc]->getNumValidBlocks(); 38511308Santhony.gutierrez@amd.com assert(ret >= 0); 38611308Santhony.gutierrez@amd.com } 38711308Santhony.gutierrez@amd.com 38811308Santhony.gutierrez@amd.com return ret; 38911308Santhony.gutierrez@amd.com} 39011308Santhony.gutierrez@amd.com 39111308Santhony.gutierrez@amd.comvoid 3928683SN/ACacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 3936782SN/A{ 39411061Snilay@cs.wisc.edu uint64_t warmedUpBlocks = 0; 39511061Snilay@cs.wisc.edu uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets * 39611061Snilay@cs.wisc.edu (uint64_t)m_cache_assoc; 3978683SN/A 3987039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 3997039SN/A for (int j = 0; j < m_cache_assoc; j++) { 4008683SN/A if (m_cache[i][j] != NULL) { 4018683SN/A AccessPermission perm = m_cache[i][j]->m_Permission; 4028683SN/A RubyRequestType request_type = RubyRequestType_NULL; 4038683SN/A if (perm == AccessPermission_Read_Only) { 4048683SN/A if (m_is_instruction_only_cache) { 4058683SN/A request_type = RubyRequestType_IFETCH; 4068683SN/A } else { 4078683SN/A request_type = RubyRequestType_LD; 4088683SN/A } 4098683SN/A } else if (perm == AccessPermission_Read_Write) { 4108683SN/A request_type = RubyRequestType_ST; 4117039SN/A } 4127039SN/A 4138683SN/A if (request_type != RubyRequestType_NULL) { 41411025Snilay@cs.wisc.edu tr->addRecord(cntrl, m_cache[i][j]->m_Address, 4158683SN/A 0, request_type, 4168683SN/A m_replacementPolicy_ptr->getLastAccess(i, j), 4178683SN/A m_cache[i][j]->getDataBlk()); 4188683SN/A warmedUpBlocks++; 4198683SN/A } 4207039SN/A } 4216782SN/A } 4226782SN/A } 4238683SN/A 4248937SN/A DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" 4258683SN/A "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, 42611061Snilay@cs.wisc.edu totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0); 4276782SN/A} 4286782SN/A 4297039SN/Avoid 4307039SN/ACacheMemory::print(ostream& out) const 4316782SN/A{ 43210080SN/A out << "Cache dump: " << name() << endl; 4337039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 4347039SN/A for (int j = 0; j < m_cache_assoc; j++) { 4357039SN/A if (m_cache[i][j] != NULL) { 4367039SN/A out << " Index: " << i 4377039SN/A << " way: " << j 4387039SN/A << " entry: " << *m_cache[i][j] << endl; 4397039SN/A } else { 4407039SN/A out << " Index: " << i 4417039SN/A << " way: " << j 4427039SN/A << " entry: NULL" << endl; 4437039SN/A } 4447039SN/A } 4456782SN/A } 4466782SN/A} 4476782SN/A 4487039SN/Avoid 4497039SN/ACacheMemory::printData(ostream& out) const 4506782SN/A{ 4517039SN/A out << "printData() not supported" << endl; 4526782SN/A} 4536782SN/A 4547039SN/Avoid 45511025Snilay@cs.wisc.eduCacheMemory::setLocked(Addr address, int context) 4567039SN/A{ 45711118Snilay@cs.wisc.edu DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", address, context); 45811025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 45911061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 4607039SN/A int loc = findTagInSet(cacheSet, address); 4617039SN/A assert(loc != -1); 46211059Snilay@cs.wisc.edu m_cache[cacheSet][loc]->setLocked(context); 4636782SN/A} 4646782SN/A 4657039SN/Avoid 46611025Snilay@cs.wisc.eduCacheMemory::clearLocked(Addr address) 4676782SN/A{ 46811118Snilay@cs.wisc.edu DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", address); 46911025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 47011061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 4717039SN/A int loc = findTagInSet(cacheSet, address); 4727039SN/A assert(loc != -1); 47311059Snilay@cs.wisc.edu m_cache[cacheSet][loc]->clearLocked(); 4746782SN/A} 4756782SN/A 4766782SN/Abool 47711025Snilay@cs.wisc.eduCacheMemory::isLocked(Addr address, int context) 4786782SN/A{ 47911025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 48011061Snilay@cs.wisc.edu int64_t cacheSet = addressToCacheSet(address); 4817039SN/A int loc = findTagInSet(cacheSet, address); 4827039SN/A assert(loc != -1); 48311118Snilay@cs.wisc.edu DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n", 4847839SN/A address, m_cache[cacheSet][loc]->m_locked, context); 48511059Snilay@cs.wisc.edu return m_cache[cacheSet][loc]->isLocked(context); 4866782SN/A} 4876782SN/A 4889104SN/Avoid 4899692SN/ACacheMemory::regStats() 4909692SN/A{ 4919692SN/A m_demand_hits 4929692SN/A .name(name() + ".demand_hits") 4939692SN/A .desc("Number of cache demand hits") 4949692SN/A ; 4959692SN/A 4969692SN/A m_demand_misses 4979692SN/A .name(name() + ".demand_misses") 4989692SN/A .desc("Number of cache demand misses") 4999692SN/A ; 5009692SN/A 5019692SN/A m_demand_accesses 5029692SN/A .name(name() + ".demand_accesses") 5039692SN/A .desc("Number of cache demand accesses") 5049692SN/A ; 5059692SN/A 5069692SN/A m_demand_accesses = m_demand_hits + m_demand_misses; 5079692SN/A 5089692SN/A m_sw_prefetches 5099692SN/A .name(name() + ".total_sw_prefetches") 5109692SN/A .desc("Number of software prefetches") 5119692SN/A .flags(Stats::nozero) 5129692SN/A ; 5139692SN/A 5149692SN/A m_hw_prefetches 5159692SN/A .name(name() + ".total_hw_prefetches") 5169692SN/A .desc("Number of hardware prefetches") 5179692SN/A .flags(Stats::nozero) 5189692SN/A ; 5199692SN/A 5209692SN/A m_prefetches 5219692SN/A .name(name() + ".total_prefetches") 5229692SN/A .desc("Number of prefetches") 5239692SN/A .flags(Stats::nozero) 5249692SN/A ; 5259692SN/A 5269692SN/A m_prefetches = m_sw_prefetches + m_hw_prefetches; 5279692SN/A 5289692SN/A m_accessModeType 5299692SN/A .init(RubyRequestType_NUM) 5309692SN/A .name(name() + ".access_mode") 5319692SN/A .flags(Stats::pdf | Stats::total) 5329692SN/A ; 5339692SN/A for (int i = 0; i < RubyAccessMode_NUM; i++) { 5349692SN/A m_accessModeType 5359692SN/A .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) 5369692SN/A .flags(Stats::nozero) 5379692SN/A ; 5389692SN/A } 5399692SN/A 5409692SN/A numDataArrayReads 5419692SN/A .name(name() + ".num_data_array_reads") 5429692SN/A .desc("number of data array reads") 5439692SN/A .flags(Stats::nozero) 5449692SN/A ; 5459692SN/A 5469692SN/A numDataArrayWrites 5479692SN/A .name(name() + ".num_data_array_writes") 5489692SN/A .desc("number of data array writes") 5499692SN/A .flags(Stats::nozero) 5509692SN/A ; 5519692SN/A 5529692SN/A numTagArrayReads 5539692SN/A .name(name() + ".num_tag_array_reads") 5549692SN/A .desc("number of tag array reads") 5559692SN/A .flags(Stats::nozero) 5569692SN/A ; 5579692SN/A 5589692SN/A numTagArrayWrites 5599692SN/A .name(name() + ".num_tag_array_writes") 5609692SN/A .desc("number of tag array writes") 5619692SN/A .flags(Stats::nozero) 5629692SN/A ; 5639692SN/A 5649692SN/A numTagArrayStalls 5659692SN/A .name(name() + ".num_tag_array_stalls") 5669692SN/A .desc("number of stalls caused by tag array") 5679692SN/A .flags(Stats::nozero) 5689692SN/A ; 5699692SN/A 5709692SN/A numDataArrayStalls 5719692SN/A .name(name() + ".num_data_array_stalls") 5729692SN/A .desc("number of stalls caused by data array") 5739692SN/A .flags(Stats::nozero) 5749692SN/A ; 5759692SN/A} 5769692SN/A 57710978Sdavid.hashe@amd.com// assumption: SLICC generated files will only call this function 57810978Sdavid.hashe@amd.com// once **all** resources are granted 5799692SN/Avoid 58011025Snilay@cs.wisc.eduCacheMemory::recordRequestType(CacheRequestType requestType, Addr addr) 5819692SN/A{ 5829104SN/A DPRINTF(RubyStats, "Recorded statistic: %s\n", 5839104SN/A CacheRequestType_to_string(requestType)); 5849104SN/A switch(requestType) { 5859104SN/A case CacheRequestType_DataArrayRead: 58610978Sdavid.hashe@amd.com if (m_resource_stalls) 58710978Sdavid.hashe@amd.com dataArray.reserve(addressToCacheSet(addr)); 5889104SN/A numDataArrayReads++; 5899104SN/A return; 5909104SN/A case CacheRequestType_DataArrayWrite: 59110978Sdavid.hashe@amd.com if (m_resource_stalls) 59210978Sdavid.hashe@amd.com dataArray.reserve(addressToCacheSet(addr)); 5939104SN/A numDataArrayWrites++; 5949104SN/A return; 5959104SN/A case CacheRequestType_TagArrayRead: 59610978Sdavid.hashe@amd.com if (m_resource_stalls) 59710978Sdavid.hashe@amd.com tagArray.reserve(addressToCacheSet(addr)); 5989104SN/A numTagArrayReads++; 5999104SN/A return; 6009104SN/A case CacheRequestType_TagArrayWrite: 60110978Sdavid.hashe@amd.com if (m_resource_stalls) 60210978Sdavid.hashe@amd.com tagArray.reserve(addressToCacheSet(addr)); 6039104SN/A numTagArrayWrites++; 6049104SN/A return; 6059104SN/A default: 6069104SN/A warn("CacheMemory access_type not found: %s", 6079104SN/A CacheRequestType_to_string(requestType)); 6089104SN/A } 6099104SN/A} 6109104SN/A 6119105SN/Abool 61211025Snilay@cs.wisc.eduCacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr) 6139105SN/A{ 6149105SN/A if (!m_resource_stalls) { 6159105SN/A return true; 6169105SN/A } 6179105SN/A 6189105SN/A if (res == CacheResourceType_TagArray) { 6199105SN/A if (tagArray.tryAccess(addressToCacheSet(addr))) return true; 6209105SN/A else { 6219692SN/A DPRINTF(RubyResourceStalls, 62211118Snilay@cs.wisc.edu "Tag array stall on addr %#x in set %d\n", 6239692SN/A addr, addressToCacheSet(addr)); 6249105SN/A numTagArrayStalls++; 6259105SN/A return false; 6269105SN/A } 6279105SN/A } else if (res == CacheResourceType_DataArray) { 6289105SN/A if (dataArray.tryAccess(addressToCacheSet(addr))) return true; 6299105SN/A else { 6309692SN/A DPRINTF(RubyResourceStalls, 63111118Snilay@cs.wisc.edu "Data array stall on addr %#x in set %d\n", 6329692SN/A addr, addressToCacheSet(addr)); 6339105SN/A numDataArrayStalls++; 6349105SN/A return false; 6359105SN/A } 6369105SN/A } else { 6379105SN/A assert(false); 6389105SN/A return true; 6399105SN/A } 6409105SN/A} 64110980Sdavid.hashe@amd.com 64210980Sdavid.hashe@amd.combool 64311061Snilay@cs.wisc.eduCacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc) 64410980Sdavid.hashe@amd.com{ 64510980Sdavid.hashe@amd.com return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid); 64610980Sdavid.hashe@amd.com} 64710980Sdavid.hashe@amd.com 64810980Sdavid.hashe@amd.combool 64911061Snilay@cs.wisc.eduCacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc) 65010980Sdavid.hashe@amd.com{ 65110980Sdavid.hashe@amd.com return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy); 65210980Sdavid.hashe@amd.com} 653