CacheMemory.cc revision 10973
16782SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310973Sdavid.hashe@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 46782SN/A * All rights reserved. 56782SN/A * 66782SN/A * Redistribution and use in source and binary forms, with or without 76782SN/A * modification, are permitted provided that the following conditions are 86782SN/A * met: redistributions of source code must retain the above copyright 96782SN/A * notice, this list of conditions and the following disclaimer; 106782SN/A * redistributions in binary form must reproduce the above copyright 116782SN/A * notice, this list of conditions and the following disclaimer in the 126782SN/A * documentation and/or other materials provided with the distribution; 136782SN/A * neither the name of the copyright holders nor the names of its 146782SN/A * contributors may be used to endorse or promote products derived from 156782SN/A * this software without specific prior written permission. 166782SN/A * 176782SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186782SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196782SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206782SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216782SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226782SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236782SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246782SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256782SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266782SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276782SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286782SN/A */ 296782SN/A 307056SN/A#include "base/intmath.hh" 318232SN/A#include "debug/RubyCache.hh" 328937SN/A#include "debug/RubyCacheTrace.hh" 339105SN/A#include "debug/RubyResourceStalls.hh" 349104SN/A#include "debug/RubyStats.hh" 358683SN/A#include "mem/protocol/AccessPermission.hh" 3610301Snilay@cs.wisc.edu#include "mem/ruby/structures/CacheMemory.hh" 378683SN/A#include "mem/ruby/system/System.hh" 386782SN/A 397055SN/Ausing namespace std; 407055SN/A 417039SN/Aostream& 427039SN/Aoperator<<(ostream& out, const CacheMemory& obj) 436782SN/A{ 447039SN/A obj.print(out); 457039SN/A out << flush; 467039SN/A return out; 476782SN/A} 486782SN/A 496876SN/ACacheMemory * 506876SN/ARubyCacheParams::create() 516782SN/A{ 526876SN/A return new CacheMemory(this); 536782SN/A} 546782SN/A 556876SN/ACacheMemory::CacheMemory(const Params *p) 569105SN/A : SimObject(p), 5710919Sbrandon.potter@amd.com dataArray(p->dataArrayBanks, p->dataAccessLatency, 5810919Sbrandon.potter@amd.com p->start_index_bit, p->ruby_system), 5910919Sbrandon.potter@amd.com tagArray(p->tagArrayBanks, p->tagAccessLatency, 6010919Sbrandon.potter@amd.com p->start_index_bit, p->ruby_system) 616782SN/A{ 626882SN/A m_cache_size = p->size; 636876SN/A m_latency = p->latency; 646876SN/A m_cache_assoc = p->assoc; 6510970Sdavid.hashe@amd.com m_replacementPolicy_ptr = p->replacement_policy; 667564SN/A m_start_index_bit = p->start_index_bit; 678653SN/A m_is_instruction_only_cache = p->is_icache; 689105SN/A m_resource_stalls = p->resourceStalls; 696876SN/A} 706876SN/A 717039SN/Avoid 727039SN/ACacheMemory::init() 736876SN/A{ 747039SN/A m_cache_num_sets = (m_cache_size / m_cache_assoc) / 757039SN/A RubySystem::getBlockSizeBytes(); 766882SN/A assert(m_cache_num_sets > 1); 777056SN/A m_cache_num_set_bits = floorLog2(m_cache_num_sets); 786882SN/A assert(m_cache_num_set_bits > 0); 797039SN/A 807454SN/A m_cache.resize(m_cache_num_sets); 817039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 827454SN/A m_cache[i].resize(m_cache_assoc); 837039SN/A for (int j = 0; j < m_cache_assoc; j++) { 847039SN/A m_cache[i][j] = NULL; 857039SN/A } 866782SN/A } 876782SN/A} 886782SN/A 896782SN/ACacheMemory::~CacheMemory() 906782SN/A{ 917039SN/A if (m_replacementPolicy_ptr != NULL) 927039SN/A delete m_replacementPolicy_ptr; 937039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 947039SN/A for (int j = 0; j < m_cache_assoc; j++) { 957039SN/A delete m_cache[i][j]; 967039SN/A } 976783SN/A } 986782SN/A} 996782SN/A 1006782SN/A// convert a Address to its location in the cache 10110314Snilay@cs.wisc.eduint64 1027039SN/ACacheMemory::addressToCacheSet(const Address& address) const 1036782SN/A{ 1047039SN/A assert(address == line_address(address)); 1057564SN/A return address.bitSelect(m_start_index_bit, 1067564SN/A m_start_index_bit + m_cache_num_set_bits - 1); 1076782SN/A} 1086782SN/A 1096782SN/A// Given a cache index: returns the index of the tag in a set. 1106782SN/A// returns -1 if the tag is not found. 1117039SN/Aint 11210314Snilay@cs.wisc.eduCacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const 1136782SN/A{ 1147039SN/A assert(tag == line_address(tag)); 1157039SN/A // search the set for the tags 1167039SN/A m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); 1177039SN/A if (it != m_tag_index.end()) 1187039SN/A if (m_cache[cacheSet][it->second]->m_Permission != 1197039SN/A AccessPermission_NotPresent) 1207039SN/A return it->second; 1217039SN/A return -1; // Not found 1226782SN/A} 1236782SN/A 1246782SN/A// Given a cache index: returns the index of the tag in a set. 1256782SN/A// returns -1 if the tag is not found. 1267039SN/Aint 12710314Snilay@cs.wisc.eduCacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, 1287039SN/A const Address& tag) const 1296782SN/A{ 1307039SN/A assert(tag == line_address(tag)); 1317039SN/A // search the set for the tags 1327039SN/A m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); 1337039SN/A if (it != m_tag_index.end()) 1347039SN/A return it->second; 1357039SN/A return -1; // Not found 1366782SN/A} 1376782SN/A 13810973Sdavid.hashe@amd.com// Given an unique cache block identifier (idx): return the valid address 13910973Sdavid.hashe@amd.com// stored by the cache block. If the block is invalid/notpresent, the 14010973Sdavid.hashe@amd.com// function returns the 0 address 14110973Sdavid.hashe@amd.comAddress 14210973Sdavid.hashe@amd.comCacheMemory::getAddressAtIdx(int idx) const 14310973Sdavid.hashe@amd.com{ 14410973Sdavid.hashe@amd.com Address tmp(0); 14510973Sdavid.hashe@amd.com 14610973Sdavid.hashe@amd.com int set = idx / m_cache_assoc; 14710973Sdavid.hashe@amd.com assert(set < m_cache_num_sets); 14810973Sdavid.hashe@amd.com 14910973Sdavid.hashe@amd.com int way = idx - set * m_cache_assoc; 15010973Sdavid.hashe@amd.com assert (way < m_cache_assoc); 15110973Sdavid.hashe@amd.com 15210973Sdavid.hashe@amd.com AbstractCacheEntry* entry = m_cache[set][way]; 15310973Sdavid.hashe@amd.com if (entry == NULL || 15410973Sdavid.hashe@amd.com entry->m_Permission == AccessPermission_Invalid || 15510973Sdavid.hashe@amd.com entry->m_Permission == AccessPermission_NotPresent) { 15610973Sdavid.hashe@amd.com return tmp; 15710973Sdavid.hashe@amd.com } 15810973Sdavid.hashe@amd.com return entry->m_Address; 15910973Sdavid.hashe@amd.com} 16010973Sdavid.hashe@amd.com 1617039SN/Abool 1628165SN/ACacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, 1637039SN/A DataBlock*& data_ptr) 1646782SN/A{ 1657039SN/A assert(address == line_address(address)); 1667780SN/A DPRINTF(RubyCache, "address: %s\n", address); 16710314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 1687039SN/A int loc = findTagInSet(cacheSet, address); 1697039SN/A if (loc != -1) { 1707039SN/A // Do we even have a tag match? 1717039SN/A AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 1729171SN/A m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 1737039SN/A data_ptr = &(entry->getDataBlk()); 1746782SN/A 1757039SN/A if (entry->m_Permission == AccessPermission_Read_Write) { 1767039SN/A return true; 1777039SN/A } 1787039SN/A if ((entry->m_Permission == AccessPermission_Read_Only) && 1798165SN/A (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { 1807039SN/A return true; 1817039SN/A } 1827039SN/A // The line must not be accessible 1836782SN/A } 1847039SN/A data_ptr = NULL; 1857039SN/A return false; 1866782SN/A} 1876782SN/A 1887039SN/Abool 1898165SN/ACacheMemory::testCacheAccess(const Address& address, RubyRequestType type, 1907039SN/A DataBlock*& data_ptr) 1916782SN/A{ 1927039SN/A assert(address == line_address(address)); 1937780SN/A DPRINTF(RubyCache, "address: %s\n", address); 19410314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 1957039SN/A int loc = findTagInSet(cacheSet, address); 1966782SN/A 1977039SN/A if (loc != -1) { 1987039SN/A // Do we even have a tag match? 1997039SN/A AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 2009171SN/A m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 2017039SN/A data_ptr = &(entry->getDataBlk()); 2027039SN/A 2037039SN/A return m_cache[cacheSet][loc]->m_Permission != 2047039SN/A AccessPermission_NotPresent; 2057039SN/A } 2067039SN/A 2077039SN/A data_ptr = NULL; 2087039SN/A return false; 2096782SN/A} 2106782SN/A 2116782SN/A// tests to see if an address is present in the cache 2127039SN/Abool 2137039SN/ACacheMemory::isTagPresent(const Address& address) const 2146782SN/A{ 2157039SN/A assert(address == line_address(address)); 21610314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 2177039SN/A int loc = findTagInSet(cacheSet, address); 2186782SN/A 2197039SN/A if (loc == -1) { 2207039SN/A // We didn't find the tag 2217780SN/A DPRINTF(RubyCache, "No tag match for address: %s\n", address); 2227039SN/A return false; 2237039SN/A } 2247780SN/A DPRINTF(RubyCache, "address: %s found\n", address); 2257039SN/A return true; 2266782SN/A} 2276782SN/A 2286782SN/A// Returns true if there is: 2296782SN/A// a) a tag match on this address or there is 2306782SN/A// b) an unused line in the same cache "way" 2317039SN/Abool 2327039SN/ACacheMemory::cacheAvail(const Address& address) const 2336782SN/A{ 2347039SN/A assert(address == line_address(address)); 2356782SN/A 23610314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 2376782SN/A 2387039SN/A for (int i = 0; i < m_cache_assoc; i++) { 2397039SN/A AbstractCacheEntry* entry = m_cache[cacheSet][i]; 2407039SN/A if (entry != NULL) { 2417039SN/A if (entry->m_Address == address || 2427039SN/A entry->m_Permission == AccessPermission_NotPresent) { 2437039SN/A // Already in the cache or we found an empty entry 2447039SN/A return true; 2457039SN/A } 2467039SN/A } else { 2477039SN/A return true; 2487039SN/A } 2496782SN/A } 2507039SN/A return false; 2516782SN/A} 2526782SN/A 2537839SN/AAbstractCacheEntry* 2547039SN/ACacheMemory::allocate(const Address& address, AbstractCacheEntry* entry) 2556782SN/A{ 2567039SN/A assert(address == line_address(address)); 2577039SN/A assert(!isTagPresent(address)); 2587039SN/A assert(cacheAvail(address)); 2597780SN/A DPRINTF(RubyCache, "address: %s\n", address); 2606782SN/A 2617039SN/A // Find the first open slot 26210314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 2637454SN/A std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; 2647039SN/A for (int i = 0; i < m_cache_assoc; i++) { 2657039SN/A if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { 2667039SN/A set[i] = entry; // Init entry 2677039SN/A set[i]->m_Address = address; 2687039SN/A set[i]->m_Permission = AccessPermission_Invalid; 2697039SN/A DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n", 2707039SN/A address); 2717839SN/A set[i]->m_locked = -1; 2727039SN/A m_tag_index[address] = i; 2736782SN/A 2749171SN/A m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 2756782SN/A 2767839SN/A return entry; 2777039SN/A } 2786782SN/A } 2797805SN/A panic("Allocate didn't find an available entry"); 2806782SN/A} 2816782SN/A 2827039SN/Avoid 2837039SN/ACacheMemory::deallocate(const Address& address) 2846782SN/A{ 2857039SN/A assert(address == line_address(address)); 2867039SN/A assert(isTagPresent(address)); 2877780SN/A DPRINTF(RubyCache, "address: %s\n", address); 28810314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 2897039SN/A int loc = findTagInSet(cacheSet, address); 2907039SN/A if (loc != -1) { 2917039SN/A delete m_cache[cacheSet][loc]; 2927039SN/A m_cache[cacheSet][loc] = NULL; 2937039SN/A m_tag_index.erase(address); 2947039SN/A } 2956782SN/A} 2966782SN/A 2976782SN/A// Returns with the physical address of the conflicting cache line 2987039SN/AAddress 2997039SN/ACacheMemory::cacheProbe(const Address& address) const 3006782SN/A{ 3017039SN/A assert(address == line_address(address)); 3027039SN/A assert(!cacheAvail(address)); 3036782SN/A 30410314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 3057039SN/A return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> 3067039SN/A m_Address; 3076782SN/A} 3086782SN/A 3096782SN/A// looks an address up in the cache 3107839SN/AAbstractCacheEntry* 3117039SN/ACacheMemory::lookup(const Address& address) 3126782SN/A{ 3137039SN/A assert(address == line_address(address)); 31410314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 3157039SN/A int loc = findTagInSet(cacheSet, address); 3167839SN/A if(loc == -1) return NULL; 3177839SN/A return m_cache[cacheSet][loc]; 3186782SN/A} 3196782SN/A 3206782SN/A// looks an address up in the cache 3217839SN/Aconst AbstractCacheEntry* 3227039SN/ACacheMemory::lookup(const Address& address) const 3236782SN/A{ 3247039SN/A assert(address == line_address(address)); 32510314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 3267039SN/A int loc = findTagInSet(cacheSet, address); 3277839SN/A if(loc == -1) return NULL; 3287839SN/A return m_cache[cacheSet][loc]; 3296782SN/A} 3306782SN/A 3316782SN/A// Sets the most recently used bit for a cache block 3327039SN/Avoid 3337039SN/ACacheMemory::setMRU(const Address& address) 3346782SN/A{ 33510314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 3368828SN/A int loc = findTagInSet(cacheSet, address); 3376782SN/A 3388828SN/A if(loc != -1) 3399171SN/A m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 3406782SN/A} 3416782SN/A 3427039SN/Avoid 3438683SN/ACacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 3446782SN/A{ 3458683SN/A uint64 warmedUpBlocks = 0; 3468683SN/A uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets 3478683SN/A * (uint64)m_cache_assoc; 3488683SN/A 3497039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 3507039SN/A for (int j = 0; j < m_cache_assoc; j++) { 3518683SN/A if (m_cache[i][j] != NULL) { 3528683SN/A AccessPermission perm = m_cache[i][j]->m_Permission; 3538683SN/A RubyRequestType request_type = RubyRequestType_NULL; 3548683SN/A if (perm == AccessPermission_Read_Only) { 3558683SN/A if (m_is_instruction_only_cache) { 3568683SN/A request_type = RubyRequestType_IFETCH; 3578683SN/A } else { 3588683SN/A request_type = RubyRequestType_LD; 3598683SN/A } 3608683SN/A } else if (perm == AccessPermission_Read_Write) { 3618683SN/A request_type = RubyRequestType_ST; 3627039SN/A } 3637039SN/A 3648683SN/A if (request_type != RubyRequestType_NULL) { 3658683SN/A tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(), 3668683SN/A 0, request_type, 3678683SN/A m_replacementPolicy_ptr->getLastAccess(i, j), 3688683SN/A m_cache[i][j]->getDataBlk()); 3698683SN/A warmedUpBlocks++; 3708683SN/A } 3717039SN/A } 3726782SN/A } 3736782SN/A } 3748683SN/A 3758937SN/A DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" 3768683SN/A "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, 3778683SN/A (uint64)m_cache_num_sets * (uint64)m_cache_assoc, 3788683SN/A (float(warmedUpBlocks)/float(totalBlocks))*100.0); 3796782SN/A} 3806782SN/A 3817039SN/Avoid 3827039SN/ACacheMemory::print(ostream& out) const 3836782SN/A{ 38410080SN/A out << "Cache dump: " << name() << endl; 3857039SN/A for (int i = 0; i < m_cache_num_sets; i++) { 3867039SN/A for (int j = 0; j < m_cache_assoc; j++) { 3877039SN/A if (m_cache[i][j] != NULL) { 3887039SN/A out << " Index: " << i 3897039SN/A << " way: " << j 3907039SN/A << " entry: " << *m_cache[i][j] << endl; 3917039SN/A } else { 3927039SN/A out << " Index: " << i 3937039SN/A << " way: " << j 3947039SN/A << " entry: NULL" << endl; 3957039SN/A } 3967039SN/A } 3976782SN/A } 3986782SN/A} 3996782SN/A 4007039SN/Avoid 4017039SN/ACacheMemory::printData(ostream& out) const 4026782SN/A{ 4037039SN/A out << "printData() not supported" << endl; 4046782SN/A} 4056782SN/A 4067039SN/Avoid 4077039SN/ACacheMemory::setLocked(const Address& address, int context) 4087039SN/A{ 4097039SN/A DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); 4107039SN/A assert(address == line_address(address)); 41110314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 4127039SN/A int loc = findTagInSet(cacheSet, address); 4137039SN/A assert(loc != -1); 4147839SN/A m_cache[cacheSet][loc]->m_locked = context; 4156782SN/A} 4166782SN/A 4177039SN/Avoid 4187039SN/ACacheMemory::clearLocked(const Address& address) 4196782SN/A{ 4207039SN/A DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); 4217039SN/A assert(address == line_address(address)); 42210314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 4237039SN/A int loc = findTagInSet(cacheSet, address); 4247039SN/A assert(loc != -1); 4257839SN/A m_cache[cacheSet][loc]->m_locked = -1; 4266782SN/A} 4276782SN/A 4286782SN/Abool 4296782SN/ACacheMemory::isLocked(const Address& address, int context) 4306782SN/A{ 4317039SN/A assert(address == line_address(address)); 43210314Snilay@cs.wisc.edu int64 cacheSet = addressToCacheSet(address); 4337039SN/A int loc = findTagInSet(cacheSet, address); 4347039SN/A assert(loc != -1); 4357039SN/A DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", 4367839SN/A address, m_cache[cacheSet][loc]->m_locked, context); 4377839SN/A return m_cache[cacheSet][loc]->m_locked == context; 4386782SN/A} 4396782SN/A 4409104SN/Avoid 4419692SN/ACacheMemory::regStats() 4429692SN/A{ 4439692SN/A m_demand_hits 4449692SN/A .name(name() + ".demand_hits") 4459692SN/A .desc("Number of cache demand hits") 4469692SN/A ; 4479692SN/A 4489692SN/A m_demand_misses 4499692SN/A .name(name() + ".demand_misses") 4509692SN/A .desc("Number of cache demand misses") 4519692SN/A ; 4529692SN/A 4539692SN/A m_demand_accesses 4549692SN/A .name(name() + ".demand_accesses") 4559692SN/A .desc("Number of cache demand accesses") 4569692SN/A ; 4579692SN/A 4589692SN/A m_demand_accesses = m_demand_hits + m_demand_misses; 4599692SN/A 4609692SN/A m_sw_prefetches 4619692SN/A .name(name() + ".total_sw_prefetches") 4629692SN/A .desc("Number of software prefetches") 4639692SN/A .flags(Stats::nozero) 4649692SN/A ; 4659692SN/A 4669692SN/A m_hw_prefetches 4679692SN/A .name(name() + ".total_hw_prefetches") 4689692SN/A .desc("Number of hardware prefetches") 4699692SN/A .flags(Stats::nozero) 4709692SN/A ; 4719692SN/A 4729692SN/A m_prefetches 4739692SN/A .name(name() + ".total_prefetches") 4749692SN/A .desc("Number of prefetches") 4759692SN/A .flags(Stats::nozero) 4769692SN/A ; 4779692SN/A 4789692SN/A m_prefetches = m_sw_prefetches + m_hw_prefetches; 4799692SN/A 4809692SN/A m_accessModeType 4819692SN/A .init(RubyRequestType_NUM) 4829692SN/A .name(name() + ".access_mode") 4839692SN/A .flags(Stats::pdf | Stats::total) 4849692SN/A ; 4859692SN/A for (int i = 0; i < RubyAccessMode_NUM; i++) { 4869692SN/A m_accessModeType 4879692SN/A .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) 4889692SN/A .flags(Stats::nozero) 4899692SN/A ; 4909692SN/A } 4919692SN/A 4929692SN/A numDataArrayReads 4939692SN/A .name(name() + ".num_data_array_reads") 4949692SN/A .desc("number of data array reads") 4959692SN/A .flags(Stats::nozero) 4969692SN/A ; 4979692SN/A 4989692SN/A numDataArrayWrites 4999692SN/A .name(name() + ".num_data_array_writes") 5009692SN/A .desc("number of data array writes") 5019692SN/A .flags(Stats::nozero) 5029692SN/A ; 5039692SN/A 5049692SN/A numTagArrayReads 5059692SN/A .name(name() + ".num_tag_array_reads") 5069692SN/A .desc("number of tag array reads") 5079692SN/A .flags(Stats::nozero) 5089692SN/A ; 5099692SN/A 5109692SN/A numTagArrayWrites 5119692SN/A .name(name() + ".num_tag_array_writes") 5129692SN/A .desc("number of tag array writes") 5139692SN/A .flags(Stats::nozero) 5149692SN/A ; 5159692SN/A 5169692SN/A numTagArrayStalls 5179692SN/A .name(name() + ".num_tag_array_stalls") 5189692SN/A .desc("number of stalls caused by tag array") 5199692SN/A .flags(Stats::nozero) 5209692SN/A ; 5219692SN/A 5229692SN/A numDataArrayStalls 5239692SN/A .name(name() + ".num_data_array_stalls") 5249692SN/A .desc("number of stalls caused by data array") 5259692SN/A .flags(Stats::nozero) 5269692SN/A ; 5279692SN/A} 5289692SN/A 5299692SN/Avoid 5309692SN/ACacheMemory::recordRequestType(CacheRequestType requestType) 5319692SN/A{ 5329104SN/A DPRINTF(RubyStats, "Recorded statistic: %s\n", 5339104SN/A CacheRequestType_to_string(requestType)); 5349104SN/A switch(requestType) { 5359104SN/A case CacheRequestType_DataArrayRead: 5369104SN/A numDataArrayReads++; 5379104SN/A return; 5389104SN/A case CacheRequestType_DataArrayWrite: 5399104SN/A numDataArrayWrites++; 5409104SN/A return; 5419104SN/A case CacheRequestType_TagArrayRead: 5429104SN/A numTagArrayReads++; 5439104SN/A return; 5449104SN/A case CacheRequestType_TagArrayWrite: 5459104SN/A numTagArrayWrites++; 5469104SN/A return; 5479104SN/A default: 5489104SN/A warn("CacheMemory access_type not found: %s", 5499104SN/A CacheRequestType_to_string(requestType)); 5509104SN/A } 5519104SN/A} 5529104SN/A 5539105SN/Abool 5549105SN/ACacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) 5559105SN/A{ 5569105SN/A if (!m_resource_stalls) { 5579105SN/A return true; 5589105SN/A } 5599105SN/A 5609105SN/A if (res == CacheResourceType_TagArray) { 5619105SN/A if (tagArray.tryAccess(addressToCacheSet(addr))) return true; 5629105SN/A else { 5639692SN/A DPRINTF(RubyResourceStalls, 5649692SN/A "Tag array stall on addr %s in set %d\n", 5659692SN/A addr, addressToCacheSet(addr)); 5669105SN/A numTagArrayStalls++; 5679105SN/A return false; 5689105SN/A } 5699105SN/A } else if (res == CacheResourceType_DataArray) { 5709105SN/A if (dataArray.tryAccess(addressToCacheSet(addr))) return true; 5719105SN/A else { 5729692SN/A DPRINTF(RubyResourceStalls, 5739692SN/A "Data array stall on addr %s in set %d\n", 5749692SN/A addr, addressToCacheSet(addr)); 5759105SN/A numDataArrayStalls++; 5769105SN/A return false; 5779105SN/A } 5789105SN/A } else { 5799105SN/A assert(false); 5809105SN/A return true; 5819105SN/A } 5829105SN/A} 583