BankedArray.hh revision 10917:c38f28fad4c3
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2012 Advanced Micro Devices, Inc. 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu * 282650Ssaidi@eecs.umich.edu * Author: Brad Beckmann 293817Ssaidi@eecs.umich.edu * 303817Ssaidi@eecs.umich.edu */ 313817Ssaidi@eecs.umich.edu 323817Ssaidi@eecs.umich.edu#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 333817Ssaidi@eecs.umich.edu#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 342650Ssaidi@eecs.umich.edu 353817Ssaidi@eecs.umich.edu#include <vector> 363817Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.edu#include "mem/ruby/common/TypeDefines.hh" 383817Ssaidi@eecs.umich.edu#include "sim/core.hh" 393919Shsul@eecs.umich.edu 402650Ssaidi@eecs.umich.educlass BankedArray 412650Ssaidi@eecs.umich.edu{ 422650Ssaidi@eecs.umich.edu private: 432982Sstever@eecs.umich.edu unsigned int banks; 443919Shsul@eecs.umich.edu Cycles accessLatency; 453921Shsul@eecs.umich.edu unsigned int bankBits; 463919Shsul@eecs.umich.edu unsigned int startIndexBit; 473919Shsul@eecs.umich.edu 483919Shsul@eecs.umich.edu class AccessRecord 492650Ssaidi@eecs.umich.edu { 503919Shsul@eecs.umich.edu public: 513919Shsul@eecs.umich.edu AccessRecord() : idx(0), startAccess(0), endAccess(0) {} 523919Shsul@eecs.umich.edu int64 idx; 533921Shsul@eecs.umich.edu Tick startAccess; 543921Shsul@eecs.umich.edu Tick endAccess; 553919Shsul@eecs.umich.edu }; 562650Ssaidi@eecs.umich.edu 573919Shsul@eecs.umich.edu // If the tick event is scheduled then the bank is busy 583919Shsul@eecs.umich.edu // otherwise, schedule the event and wait for it to complete 593919Shsul@eecs.umich.edu std::vector<AccessRecord> busyBanks; 603919Shsul@eecs.umich.edu 613919Shsul@eecs.umich.edu unsigned int mapIndexToBank(int64 idx); 623919Shsul@eecs.umich.edu 633919Shsul@eecs.umich.edu public: 643919Shsul@eecs.umich.edu BankedArray(unsigned int banks, Cycles accessLatency, 653919Shsul@eecs.umich.edu unsigned int startIndexBit); 663919Shsul@eecs.umich.edu 673919Shsul@eecs.umich.edu // Note: We try the access based on the cache index, not the address 682650Ssaidi@eecs.umich.edu // This is so we don't get aliasing on blocks being replaced 693919Shsul@eecs.umich.edu bool tryAccess(int64 idx); 703919Shsul@eecs.umich.edu 713919Shsul@eecs.umich.edu}; 723919Shsul@eecs.umich.edu 733919Shsul@eecs.umich.edu#endif 743919Shsul@eecs.umich.edu