BankedArray.hh revision 9297
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2012 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 611308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 711308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 811308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 911308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 1111308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 1211308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 1311308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 1411308Santhony.gutierrez@amd.com * this software without specific prior written permission. 1511308Santhony.gutierrez@amd.com * 1611308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * Author: Brad Beckmann 2911308Santhony.gutierrez@amd.com * 3011308Santhony.gutierrez@amd.com */ 3111308Santhony.gutierrez@amd.com 3211308Santhony.gutierrez@amd.com#ifndef __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__ 3311308Santhony.gutierrez@amd.com#define __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__ 3411308Santhony.gutierrez@amd.com 3511308Santhony.gutierrez@amd.com#include <vector> 3611308Santhony.gutierrez@amd.com 3711308Santhony.gutierrez@amd.com#include "mem/ruby/common/TypeDefines.hh" 3811308Santhony.gutierrez@amd.com#include "sim/core.hh" 3911308Santhony.gutierrez@amd.com 4011308Santhony.gutierrez@amd.comclass BankedArray 4111308Santhony.gutierrez@amd.com{ 4211308Santhony.gutierrez@amd.com private: 4311308Santhony.gutierrez@amd.com unsigned int banks; 4411308Santhony.gutierrez@amd.com Cycles accessLatency; 4511308Santhony.gutierrez@amd.com unsigned int bankBits; 4611308Santhony.gutierrez@amd.com unsigned int startIndexBit; 4711308Santhony.gutierrez@amd.com 4811308Santhony.gutierrez@amd.com class AccessRecord 4911308Santhony.gutierrez@amd.com { 5011308Santhony.gutierrez@amd.com public: 5111308Santhony.gutierrez@amd.com AccessRecord() : idx(0), startAccess(0), endAccess(0) {} 5211696Santhony.gutierrez@amd.com Index idx; 5311308Santhony.gutierrez@amd.com Tick startAccess; 5411639Salexandru.dutu@amd.com Tick endAccess; 5511308Santhony.gutierrez@amd.com }; 5611308Santhony.gutierrez@amd.com 5711308Santhony.gutierrez@amd.com // If the tick event is scheduled then the bank is busy 5811308Santhony.gutierrez@amd.com // otherwise, schedule the event and wait for it to complete 5911308Santhony.gutierrez@amd.com std::vector<AccessRecord> busyBanks; 6011639Salexandru.dutu@amd.com 6111639Salexandru.dutu@amd.com unsigned int mapIndexToBank(Index idx); 6211639Salexandru.dutu@amd.com 6311639Salexandru.dutu@amd.com public: 6411639Salexandru.dutu@amd.com BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); 6511639Salexandru.dutu@amd.com 6611639Salexandru.dutu@amd.com // Note: We try the access based on the cache index, not the address 6711639Salexandru.dutu@amd.com // This is so we don't get aliasing on blocks being replaced 6811639Salexandru.dutu@amd.com bool tryAccess(Index idx); 6911639Salexandru.dutu@amd.com 7011308Santhony.gutierrez@amd.com}; 7111639Salexandru.dutu@amd.com 7211639Salexandru.dutu@amd.com#endif 7311308Santhony.gutierrez@amd.com