BankedArray.hh revision 10441
19155SN/A/* 29155SN/A * Copyright (c) 2012 Advanced Micro Devices, Inc. 39155SN/A * All rights reserved. 49155SN/A * 59155SN/A * Redistribution and use in source and binary forms, with or without 69155SN/A * modification, are permitted provided that the following conditions are 79155SN/A * met: redistributions of source code must retain the above copyright 89155SN/A * notice, this list of conditions and the following disclaimer; 99155SN/A * redistributions in binary form must reproduce the above copyright 109155SN/A * notice, this list of conditions and the following disclaimer in the 119155SN/A * documentation and/or other materials provided with the distribution; 129155SN/A * neither the name of the copyright holders nor the names of its 139155SN/A * contributors may be used to endorse or promote products derived from 149155SN/A * this software without specific prior written permission. 159155SN/A * 169155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279155SN/A * 289155SN/A * Author: Brad Beckmann 299155SN/A * 309155SN/A */ 319105SN/A 3210441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 3310441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 349105SN/A 359105SN/A#include <vector> 369105SN/A 379105SN/A#include "mem/ruby/common/TypeDefines.hh" 389297SN/A#include "sim/core.hh" 399105SN/A 409297SN/Aclass BankedArray 419105SN/A{ 429297SN/A private: 439105SN/A unsigned int banks; 449184SN/A Cycles accessLatency; 459105SN/A unsigned int bankBits; 469105SN/A unsigned int startIndexBit; 479105SN/A 489297SN/A class AccessRecord 499105SN/A { 509297SN/A public: 519297SN/A AccessRecord() : idx(0), startAccess(0), endAccess(0) {} 5210314Snilay@cs.wisc.edu int64 idx; 539105SN/A Tick startAccess; 549297SN/A Tick endAccess; 559105SN/A }; 569105SN/A 579105SN/A // If the tick event is scheduled then the bank is busy 589105SN/A // otherwise, schedule the event and wait for it to complete 599297SN/A std::vector<AccessRecord> busyBanks; 609105SN/A 6110314Snilay@cs.wisc.edu unsigned int mapIndexToBank(int64 idx); 629105SN/A 639297SN/A public: 649184SN/A BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); 659105SN/A 669105SN/A // Note: We try the access based on the cache index, not the address 679105SN/A // This is so we don't get aliasing on blocks being replaced 6810314Snilay@cs.wisc.edu bool tryAccess(int64 idx); 699105SN/A 709105SN/A}; 719105SN/A 729105SN/A#endif 73