RubySlicc_Util.hh revision 9466:23e13ad7091f
12810SN/A/* 22810SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A */ 282810SN/A 292810SN/A/* 302810SN/A * These are the functions that exported to slicc from ruby. 312810SN/A */ 322810SN/A 332810SN/A#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__ 342810SN/A#define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__ 352810SN/A 363348SN/A#include <cassert> 373348SN/A 385338Sstever@gmail.com#include "debug/RubySlicc.hh" 395338Sstever@gmail.com#include "mem/ruby/common/Address.hh" 402810SN/A#include "mem/ruby/common/Global.hh" 412810SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 422810SN/A#include "mem/ruby/system/System.hh" 434965SN/A 445314SN/Ainline int 455314SN/Arandom(int n) 465314SN/A{ 475314SN/A return random() % n; 484965SN/A} 492810SN/A 504475SN/Ainline Time 514475SN/Aget_time() 524475SN/A{ 535034SN/A return g_system_ptr->getTime(); 545034SN/A} 555314SN/A 565314SN/Ainline Time 574628SN/Azero_time() 585034SN/A{ 595034SN/A return 0; 605034SN/A} 614626SN/A 624626SN/Ainline NodeID 635034SN/AintToID(int nodenum) 644626SN/A{ 654458SN/A NodeID id = nodenum; 662810SN/A return id; 672810SN/A} 682811SN/A 692810SN/Ainline int 702810SN/AIDToInt(NodeID id) 714458SN/A{ 724458SN/A int nodenum = id; 734458SN/A return nodenum; 742810SN/A} 752810SN/A 765314SN/Ainline Time 775314SN/AgetTimeModInt(Time time, int modulus) 785314SN/A{ 795314SN/A return time % modulus; 805314SN/A} 815314SN/A 825314SN/Ainline Time 835314SN/AgetTimePlusInt(Time addend1, int addend2) 845314SN/A{ 855314SN/A return (Time) addend1 + addend2; 865314SN/A} 872810SN/A 882810SN/Ainline Time 892810SN/AgetTimeMinusTime(Time t1, Time t2) 902810SN/A{ 912810SN/A assert(t1 >= t2); 922810SN/A return t1 - t2; 933606SN/A} 944458SN/A 954458SN/A// Return type for time_to_int is "Time" and not "int" so we get a 963013SN/A// 64-bit integer 973236SN/Ainline Time 984458SN/Atime_to_int(Time time) 994458SN/A{ 1004458SN/A return time; 1013246SN/A} 1023309SN/A 1033013SN/A// Appends an offset to an address 1042810SN/Ainline Address 1052810SN/AsetOffset(Address addr, int offset) 1063013SN/A{ 1073013SN/A Address result = addr; 1082810SN/A result.setOffset(offset); 1093013SN/A return result; 1103013SN/A} 1112810SN/A 1122810SN/A// Makes an address into a line address 1132810SN/Ainline Address 1142810SN/AmakeLineAddress(Address addr) 1152810SN/A{ 1163013SN/A Address result = addr; 1173013SN/A result.makeLineAddress(); 1183013SN/A return result; 1192897SN/A} 1202897SN/A 1213013SN/Ainline int 1222897SN/AaddressOffset(Address addr) 1234666SN/A{ 1244666SN/A return addr.getOffset(); 1254666SN/A} 1262897SN/A 1272810SN/Ainline int 1282810SN/Amod(int val, int mod) 1292844SN/A{ 1302810SN/A return val % mod; 1312858SN/A} 1322858SN/A 1332858SN/Ainline int max_tokens() 1342858SN/A{ 1352858SN/A return 1024; 1362858SN/A} 1372858SN/A 1384628SN/A/** 1392858SN/A * This function accepts an address, a data block and a packet. If the address 1402810SN/A * range for the data block contains the address which the packet needs to 1412810SN/A * read, then the data from the data block is written to the packet. True is 1422810SN/A * returned if the data block was read, otherwise false is returned. 1432810SN/A */ 1442810SN/Ainline bool 1454022SN/AtestAndRead(Address addr, DataBlock& blk, Packet *pkt) 1464022SN/A{ 1474022SN/A Address pktLineAddr(pkt->getAddr()); 1482810SN/A pktLineAddr.makeLineAddress(); 1492810SN/A 1502810SN/A Address lineAddr = addr; 1512810SN/A lineAddr.makeLineAddress(); 1522810SN/A 1532810SN/A if (pktLineAddr == lineAddr) { 1542810SN/A uint8_t *data = pkt->getPtr<uint8_t>(true); 1552810SN/A unsigned int size_in_bytes = pkt->getSize(); 1562810SN/A unsigned startByte = pkt->getAddr() - lineAddr.getAddress(); 1574871SN/A 1584871SN/A for (unsigned i = 0; i < size_in_bytes; ++i) { 1594871SN/A data[i] = blk.getByte(i + startByte); 1604871SN/A } 1614871SN/A return true; 1624871SN/A } 1634871SN/A return false; 1644871SN/A} 1654871SN/A 1664871SN/A/** 1672810SN/A * This function accepts an address, a data block and a packet. If the address 1682810SN/A * range for the data block contains the address which the packet needs to 1692810SN/A * write, then the data from the packet is written to the data block. True is 1702810SN/A * returned if the data block was written, otherwise false is returned. 1712810SN/A */ 1724871SN/Ainline bool 1732810SN/AtestAndWrite(Address addr, DataBlock& blk, Packet *pkt) 1742810SN/A{ 1752810SN/A Address pktLineAddr(pkt->getAddr()); 1762810SN/A pktLineAddr.makeLineAddress(); 1772810SN/A 1782810SN/A Address lineAddr = addr; 1794871SN/A lineAddr.makeLineAddress(); 1802810SN/A 1812810SN/A if (pktLineAddr == lineAddr) { 1824022SN/A uint8_t *data = pkt->getPtr<uint8_t>(true); 1834022SN/A unsigned int size_in_bytes = pkt->getSize(); 1844022SN/A unsigned startByte = pkt->getAddr() - lineAddr.getAddress(); 1852810SN/A 1862810SN/A for (unsigned i = 0; i < size_in_bytes; ++i) { 1872810SN/A blk.setByte(i + startByte, data[i]); 1882810SN/A } 1892810SN/A return true; 1902810SN/A } 1912810SN/A return false; 1922810SN/A} 1932810SN/A 1942810SN/A#endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__ 1952810SN/A