RubySlicc_ComponentMapping.hh revision 8485:7a9a7f2a3d46
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__ 31 32#include "mem/protocol/GenericMachineType.hh" 33#include "mem/protocol/MachineType.hh" 34#include "mem/ruby/common/Address.hh" 35#include "mem/ruby/common/Global.hh" 36#include "mem/ruby/common/NetDest.hh" 37#include "mem/ruby/system/DirectoryMemory.hh" 38#include "mem/ruby/system/MachineID.hh" 39#include "mem/ruby/system/NodeID.hh" 40 41#ifdef MACHINETYPE_L1Cache 42#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache 43#else 44#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM 45#endif 46 47#ifdef MACHINETYPE_L2Cache 48#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache 49#else 50#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM 51#endif 52 53#ifdef MACHINETYPE_L3Cache 54#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache 55#else 56#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM 57#endif 58 59#ifdef MACHINETYPE_DMA 60#define MACHINETYPE_DMA_ENUM MachineType_DMA 61#else 62#define MACHINETYPE_DMA_ENUM MachineType_NUM 63#endif 64 65// used to determine the home directory 66// returns a value between 0 and total_directories_within_the_system 67inline NodeID 68map_Address_to_DirectoryNode(const Address& addr) 69{ 70 return DirectoryMemory::mapAddressToDirectoryVersion(addr); 71} 72 73// used to determine the home directory 74// returns a value between 0 and total_directories_within_the_system 75inline MachineID 76map_Address_to_Directory(const Address &addr) 77{ 78 MachineID mach = 79 {MachineType_Directory, map_Address_to_DirectoryNode(addr)}; 80 return mach; 81} 82 83inline MachineID 84map_Address_to_DMA(const Address & addr) 85{ 86 MachineID dma = {MACHINETYPE_DMA_ENUM, 0}; 87 return dma; 88} 89 90inline NetDest 91broadcast(MachineType type) 92{ 93 NetDest dest; 94 for (int i = 0; i < MachineType_base_count(type); i++) { 95 MachineID mach = {type, i}; 96 dest.add(mach); 97 } 98 return dest; 99} 100 101inline MachineID 102mapAddressToRange(const Address & addr, MachineType type, int low_bit, 103 int num_bits) 104{ 105 MachineID mach = {type, 0}; 106 if (num_bits == 0) 107 return mach; 108 mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1); 109 return mach; 110} 111 112inline NodeID 113machineIDToNodeID(MachineID machID) 114{ 115 return machID.num; 116} 117 118inline MachineType 119machineIDToMachineType(MachineID machID) 120{ 121 return machID.type; 122} 123 124inline NodeID 125L1CacheMachIDToProcessorNum(MachineID machID) 126{ 127 assert(machID.type == MACHINETYPE_L1CACHE_ENUM); 128 return machID.num; 129} 130 131inline MachineID 132getL1MachineID(NodeID L1RubyNode) 133{ 134 MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; 135 return mach; 136} 137 138inline GenericMachineType 139ConvertMachToGenericMach(MachineType machType) 140{ 141 if (machType == MACHINETYPE_L1CACHE_ENUM) 142 return GenericMachineType_L1Cache; 143 144 if (machType == MACHINETYPE_L2CACHE_ENUM) 145 return GenericMachineType_L2Cache; 146 147 if (machType == MACHINETYPE_L3CACHE_ENUM) 148 return GenericMachineType_L3Cache; 149 150 if (machType == MachineType_Directory) 151 return GenericMachineType_Directory; 152 153 if (machType == MACHINETYPE_DMA_ENUM) 154 return GenericMachineType_DMA; 155 156 panic("cannot convert to a GenericMachineType"); 157} 158 159inline int 160machineCount(MachineType machType) 161{ 162 return MachineType_base_count(machType); 163} 164 165#endif // __MEM_RUBY_SLICC_INTERFACE_COMPONENTMAPPINGS_HH__ 166