AbstractController.hh revision 9496:28d88a0fda74
1/* 2 * Copyright (c) 2009 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <iostream> 33#include <string> 34 35#include "mem/protocol/AccessPermission.hh" 36#include "mem/ruby/common/Address.hh" 37#include "mem/ruby/common/Consumer.hh" 38#include "mem/ruby/common/DataBlock.hh" 39#include "mem/ruby/network/Network.hh" 40#include "mem/ruby/recorder/CacheRecorder.hh" 41#include "mem/ruby/system/MachineID.hh" 42#include "mem/packet.hh" 43#include "params/RubyController.hh" 44#include "sim/clocked_object.hh" 45 46class MessageBuffer; 47class Network; 48 49class AbstractController : public ClockedObject, public Consumer 50{ 51 public: 52 typedef RubyControllerParams Params; 53 AbstractController(const Params *p); 54 void init(); 55 const Params *params() const { return (const Params *)_params; } 56 virtual MessageBuffer* getMandatoryQueue() const = 0; 57 virtual const int & getVersion() const = 0; 58 virtual const std::string toString() const = 0; // returns text version of 59 // controller type 60 virtual const std::string getName() const = 0; // return instance name 61 virtual void blockOnQueue(Address, MessageBuffer*) = 0; 62 virtual void unblock(Address) = 0; 63 virtual void initNetworkPtr(Network* net_ptr) = 0; 64 virtual AccessPermission getAccessPermission(const Address& addr) = 0; 65 virtual DataBlock& getDataBlock(const Address& addr) = 0; 66 67 virtual void print(std::ostream & out) const = 0; 68 virtual void printStats(std::ostream & out) const = 0; 69 virtual void wakeup() = 0; 70 // virtual void dumpStats(std::ostream & out) = 0; 71 virtual void clearStats() = 0; 72 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 73 virtual Sequencer* getSequencer() const = 0; 74 75 //! These functions are used by ruby system to read/write the message 76 //! queues that exist with in the controller. 77 //! The boolean return value indicates if the read was performed 78 //! successfully. 79 virtual bool functionalReadBuffers(PacketPtr&) = 0; 80 //! The return value indicates the number of messages written with the 81 //! data from the packet. 82 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0; 83 84 //! Function for enqueuing a prefetch request 85 virtual void enqueuePrefetch(const Address&, const RubyRequestType&) 86 { fatal("Prefetches not implemented!");} 87 88 public: 89 MachineID getMachineID() const { return m_machineID; } 90 uint64_t getFullyBusyCycles() const { return m_fully_busy_cycles; } 91 uint64_t getRequestCount() const { return m_request_count; } 92 const std::map<std::string, uint64_t>& getRequestProfileMap() const 93 { return m_requestProfileMap; } 94 95 protected: 96 //! Profiles original cache requests including PUTs 97 void profileRequest(const std::string &request); 98 99 protected: 100 int m_transitions_per_cycle; 101 int m_buffer_size; 102 int m_recycle_latency; 103 std::string m_name; 104 NodeID m_version; 105 Network* m_net_ptr; 106 MachineID m_machineID; 107 bool m_is_blocking; 108 std::map<Address, MessageBuffer*> m_block_map; 109 typedef std::vector<MessageBuffer*> MsgVecType; 110 typedef std::map< Address, MsgVecType* > WaitingBufType; 111 WaitingBufType m_waiting_buffers; 112 int m_max_in_port_rank; 113 int m_cur_in_port_rank; 114 int m_number_of_TBEs; 115 116 //! Counter for the number of cycles when the transitions carried out 117 //! were equal to the maximum allowed 118 uint64_t m_fully_busy_cycles; 119 120 //! Map for couting requests of different types. The controller should 121 //! call requisite function for updating the count. 122 std::map<std::string, uint64_t> m_requestProfileMap; 123 uint64_t m_request_count; 124}; 125 126#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 127