AbstractController.hh revision 11025:4872dbdea907 
1/*
2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
31
32#include <exception>
33#include <iostream>
34#include <string>
35
36#include "base/callback.hh"
37#include "mem/protocol/AccessPermission.hh"
38#include "mem/ruby/common/Address.hh"
39#include "mem/ruby/common/Consumer.hh"
40#include "mem/ruby/common/DataBlock.hh"
41#include "mem/ruby/common/Histogram.hh"
42#include "mem/ruby/common/MachineID.hh"
43#include "mem/ruby/network/MessageBuffer.hh"
44#include "mem/ruby/network/Network.hh"
45#include "mem/ruby/system/CacheRecorder.hh"
46#include "mem/packet.hh"
47#include "mem/qport.hh"
48#include "params/RubyController.hh"
49#include "mem/mem_object.hh"
50
51class Network;
52
53// used to communicate that an in_port peeked the wrong message type
54class RejectException: public std::exception
55{
56    virtual const char* what() const throw()
57    { return "Port rejected message based on type"; }
58};
59
60class AbstractController : public MemObject, public Consumer
61{
62  public:
63    typedef RubyControllerParams Params;
64    AbstractController(const Params *p);
65    void init();
66    const Params *params() const { return (const Params *)_params; }
67
68    const NodeID getVersion() const { return m_machineID.getNum(); }
69    const MachineType getType() const { return m_machineID.getType(); }
70
71    void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
72
73    // return instance name
74    void blockOnQueue(Addr, MessageBuffer*);
75    void unblock(Addr);
76
77    virtual MessageBuffer* getMandatoryQueue() const = 0;
78    virtual MessageBuffer* getMemoryQueue() const = 0;
79    virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
80
81    virtual void print(std::ostream & out) const = 0;
82    virtual void wakeup() = 0;
83    virtual void resetStats() = 0;
84    virtual void regStats();
85
86    virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
87    virtual Sequencer* getSequencer() const = 0;
88
89    //! These functions are used by ruby system to read/write the data blocks
90    //! that exist with in the controller.
91    virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
92    void functionalMemoryRead(PacketPtr);
93    //! The return value indicates the number of messages written with the
94    //! data from the packet.
95    virtual int functionalWriteBuffers(PacketPtr&) = 0;
96    virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
97    int functionalMemoryWrite(PacketPtr);
98
99    //! Function for enqueuing a prefetch request
100    virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
101    { fatal("Prefetches not implemented!");}
102
103    //! Function for collating statistics from all the controllers of this
104    //! particular type. This function should only be called from the
105    //! version 0 of this controller type.
106    virtual void collateStats()
107    {fatal("collateStats() should be overridden!");}
108
109    //! Initialize the message buffers.
110    virtual void initNetQueues() = 0;
111
112    /** A function used to return the port associated with this bus object. */
113    BaseMasterPort& getMasterPort(const std::string& if_name,
114                                  PortID idx = InvalidPortID);
115
116    void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
117    void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
118                          const DataBlock &block);
119    void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
120                                 const DataBlock &block, int size);
121    void recvTimingResp(PacketPtr pkt);
122
123  public:
124    MachineID getMachineID() const { return m_machineID; }
125
126    Stats::Histogram& getDelayHist() { return m_delayHistogram; }
127    Stats::Histogram& getDelayVCHist(uint32_t index)
128    { return *(m_delayVCHistogram[index]); }
129
130  protected:
131    //! Profiles original cache requests including PUTs
132    void profileRequest(const std::string &request);
133    //! Profiles the delay associated with messages.
134    void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
135
136    void stallBuffer(MessageBuffer* buf, Addr addr);
137    void wakeUpBuffers(Addr addr);
138    void wakeUpAllBuffers(Addr addr);
139    void wakeUpAllBuffers();
140
141  protected:
142    NodeID m_version;
143    MachineID m_machineID;
144    NodeID m_clusterID;
145
146    // MasterID used by some components of gem5.
147    MasterID m_masterId;
148
149    Network* m_net_ptr;
150    bool m_is_blocking;
151    std::map<Addr, MessageBuffer*> m_block_map;
152
153    typedef std::vector<MessageBuffer*> MsgVecType;
154    typedef std::set<MessageBuffer*> MsgBufType;
155    typedef std::map<Addr, MsgVecType* > WaitingBufType;
156    WaitingBufType m_waiting_buffers;
157
158    unsigned int m_in_ports;
159    unsigned int m_cur_in_port;
160    int m_number_of_TBEs;
161    int m_transitions_per_cycle;
162    unsigned int m_buffer_size;
163    Cycles m_recycle_latency;
164
165    //! Counter for the number of cycles when the transitions carried out
166    //! were equal to the maximum allowed
167    Stats::Scalar m_fully_busy_cycles;
168
169    //! Histogram for profiling delay for the messages this controller
170    //! cares for
171    Stats::Histogram m_delayHistogram;
172    std::vector<Stats::Histogram *> m_delayVCHistogram;
173
174    //! Callback class used for collating statistics from all the
175    //! controller of this type.
176    class StatsCallback : public Callback
177    {
178      private:
179        AbstractController *ctr;
180
181      public:
182        virtual ~StatsCallback() {}
183        StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
184        void process() {ctr->collateStats();}
185    };
186
187    /**
188     * Port that forwards requests and receives responses from the
189     * memory controller.  It has a queue of packets not yet sent.
190     */
191    class MemoryPort : public QueuedMasterPort
192    {
193      private:
194        // Packet queues used to store outgoing requests and snoop responses.
195        ReqPacketQueue reqQueue;
196        SnoopRespPacketQueue snoopRespQueue;
197
198        // Controller that operates this port.
199        AbstractController *controller;
200
201      public:
202        MemoryPort(const std::string &_name, AbstractController *_controller,
203                   const std::string &_label);
204
205        // Function for receiving a timing response from the peer port.
206        // Currently the pkt is handed to the coherence controller
207        // associated with this port.
208        bool recvTimingResp(PacketPtr pkt);
209    };
210
211    /* Master port to the memory controller. */
212    MemoryPort memoryPort;
213
214    // State that is stored in packets sent to the memory controller.
215    struct SenderState : public Packet::SenderState
216    {
217        // Id of the machine from which the request originated.
218        MachineID id;
219
220        SenderState(MachineID _id) : id(_id)
221        {}
222    };
223};
224
225#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
226