AbstractController.hh revision 14184
17008Snate@binkert.org/* 213974Stiago.muck@arm.com * Copyright (c) 2017,2019 ARM Limited 312065Snikos.nikoleris@arm.com * All rights reserved. 412065Snikos.nikoleris@arm.com * 512065Snikos.nikoleris@arm.com * The license below extends only to copyright in the software and shall 612065Snikos.nikoleris@arm.com * not be construed as granting a license to any other intellectual 712065Snikos.nikoleris@arm.com * property including but not limited to intellectual property relating 812065Snikos.nikoleris@arm.com * to a hardware implementation of the functionality of the software 912065Snikos.nikoleris@arm.com * licensed hereunder. You may use the software subject to the license 1012065Snikos.nikoleris@arm.com * terms below provided that you ensure that this notice is replicated 1112065Snikos.nikoleris@arm.com * unmodified and in its entirety in all distributions of the software, 1212065Snikos.nikoleris@arm.com * modified or unmodified, in source code or in binary form. 1312065Snikos.nikoleris@arm.com * 1410524Snilay@cs.wisc.edu * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 157008Snate@binkert.org * All rights reserved. 167008Snate@binkert.org * 177008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 187008Snate@binkert.org * modification, are permitted provided that the following conditions are 197008Snate@binkert.org * met: redistributions of source code must retain the above copyright 207008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 217008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 227008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 237008Snate@binkert.org * documentation and/or other materials provided with the distribution; 247008Snate@binkert.org * neither the name of the copyright holders nor the names of its 257008Snate@binkert.org * contributors may be used to endorse or promote products derived from 267008Snate@binkert.org * this software without specific prior written permission. 277008Snate@binkert.org * 287008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397008Snate@binkert.org */ 406285Snate@binkert.org 417039Snate@binkert.org#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 427039Snate@binkert.org#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 436285Snate@binkert.org 4410963Sdavid.hashe@amd.com#include <exception> 457055Snate@binkert.org#include <iostream> 467055Snate@binkert.org#include <string> 476876Ssteve.reinhardt@amd.com 4812065Snikos.nikoleris@arm.com#include "base/addr_range.hh" 499745Snilay@cs.wisc.edu#include "base/callback.hh" 5012065Snikos.nikoleris@arm.com#include "mem/packet.hh" 5112065Snikos.nikoleris@arm.com#include "mem/qport.hh" 526506Spdudnik@gmail.com#include "mem/ruby/common/Address.hh" 537055Snate@binkert.org#include "mem/ruby/common/Consumer.hh" 548436SBrad.Beckmann@amd.com#include "mem/ruby/common/DataBlock.hh" 559497Snilay@cs.wisc.edu#include "mem/ruby/common/Histogram.hh" 5610301Snilay@cs.wisc.edu#include "mem/ruby/common/MachineID.hh" 5710301Snilay@cs.wisc.edu#include "mem/ruby/network/MessageBuffer.hh" 5814184Sgabeblack@google.com#include "mem/ruby/protocol/AccessPermission.hh" 5910301Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 607055Snate@binkert.org#include "params/RubyController.hh" 6113892Sgabeblack@google.com#include "sim/clocked_object.hh" 626285Snate@binkert.org 636285Snate@binkert.orgclass Network; 6411309Sdavid.hashe@amd.comclass GPUCoalescer; 656285Snate@binkert.org 6610963Sdavid.hashe@amd.com// used to communicate that an in_port peeked the wrong message type 6710963Sdavid.hashe@amd.comclass RejectException: public std::exception 6810963Sdavid.hashe@amd.com{ 6910963Sdavid.hashe@amd.com virtual const char* what() const throw() 7010963Sdavid.hashe@amd.com { return "Port rejected message based on type"; } 7110963Sdavid.hashe@amd.com}; 7210963Sdavid.hashe@amd.com 7313892Sgabeblack@google.comclass AbstractController : public ClockedObject, public Consumer 747039Snate@binkert.org{ 757039Snate@binkert.org public: 766876Ssteve.reinhardt@amd.com typedef RubyControllerParams Params; 778436SBrad.Beckmann@amd.com AbstractController(const Params *p); 789496Snilay@cs.wisc.edu void init(); 798257SBrad.Beckmann@amd.com const Params *params() const { return (const Params *)_params; } 809745Snilay@cs.wisc.edu 8111294Sandreas.hansson@arm.com NodeID getVersion() const { return m_machineID.getNum(); } 8211294Sandreas.hansson@arm.com MachineType getType() const { return m_machineID.getType(); } 8310078Snilay@cs.wisc.edu 849819Snilay@cs.wisc.edu void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 859819Snilay@cs.wisc.edu 869819Snilay@cs.wisc.edu // return instance name 8711025Snilay@cs.wisc.edu void blockOnQueue(Addr, MessageBuffer*); 8811448Sjthestness@gmail.com bool isBlocked(Addr) const; 8911025Snilay@cs.wisc.edu void unblock(Addr); 9011308Santhony.gutierrez@amd.com bool isBlocked(Addr); 919819Snilay@cs.wisc.edu 927039Snate@binkert.org virtual MessageBuffer* getMandatoryQueue() const = 0; 9311021Sjthestness@gmail.com virtual MessageBuffer* getMemoryQueue() const = 0; 9411025Snilay@cs.wisc.edu virtual AccessPermission getAccessPermission(const Addr &addr) = 0; 956285Snate@binkert.org 967055Snate@binkert.org virtual void print(std::ostream & out) const = 0; 977039Snate@binkert.org virtual void wakeup() = 0; 9810012Snilay@cs.wisc.edu virtual void resetStats() = 0; 9910012Snilay@cs.wisc.edu virtual void regStats(); 1009745Snilay@cs.wisc.edu 1018683Snilay@cs.wisc.edu virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 10211308Santhony.gutierrez@amd.com virtual Sequencer* getCPUSequencer() const = 0; 10311309Sdavid.hashe@amd.com virtual GPUCoalescer* getGPUCoalescer() const = 0; 1049302Snilay@cs.wisc.edu 10513974Stiago.muck@arm.com // This latency is used by the sequencer when enqueueing requests. 10613974Stiago.muck@arm.com // Different latencies may be used depending on the request type. 10713974Stiago.muck@arm.com // This is the hit latency unless the top-level cache controller 10813974Stiago.muck@arm.com // introduces additional cycles in the response path. 10913974Stiago.muck@arm.com virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type) 11013974Stiago.muck@arm.com { return m_mandatory_queue_latency; } 11113974Stiago.muck@arm.com 11210523Snilay@cs.wisc.edu //! These functions are used by ruby system to read/write the data blocks 11310523Snilay@cs.wisc.edu //! that exist with in the controller. 11411025Snilay@cs.wisc.edu virtual void functionalRead(const Addr &addr, PacketPtr) = 0; 11510524Snilay@cs.wisc.edu void functionalMemoryRead(PacketPtr); 1169302Snilay@cs.wisc.edu //! The return value indicates the number of messages written with the 1179302Snilay@cs.wisc.edu //! data from the packet. 11810524Snilay@cs.wisc.edu virtual int functionalWriteBuffers(PacketPtr&) = 0; 11911025Snilay@cs.wisc.edu virtual int functionalWrite(const Addr &addr, PacketPtr) = 0; 12010524Snilay@cs.wisc.edu int functionalMemoryWrite(PacketPtr); 1219363Snilay@cs.wisc.edu 1229363Snilay@cs.wisc.edu //! Function for enqueuing a prefetch request 12311025Snilay@cs.wisc.edu virtual void enqueuePrefetch(const Addr &, const RubyRequestType&) 1249363Snilay@cs.wisc.edu { fatal("Prefetches not implemented!");} 1259364Snilay@cs.wisc.edu 1269745Snilay@cs.wisc.edu //! Function for collating statistics from all the controllers of this 1279745Snilay@cs.wisc.edu //! particular type. This function should only be called from the 1289745Snilay@cs.wisc.edu //! version 0 of this controller type. 1299745Snilay@cs.wisc.edu virtual void collateStats() 1309745Snilay@cs.wisc.edu {fatal("collateStats() should be overridden!");} 1319745Snilay@cs.wisc.edu 13211021Sjthestness@gmail.com //! Initialize the message buffers. 13311021Sjthestness@gmail.com virtual void initNetQueues() = 0; 13410311Snilay@cs.wisc.edu 13510524Snilay@cs.wisc.edu /** A function used to return the port associated with this bus object. */ 13613784Sgabeblack@google.com Port &getPort(const std::string &if_name, 13713784Sgabeblack@google.com PortID idx=InvalidPortID); 13810524Snilay@cs.wisc.edu 13911025Snilay@cs.wisc.edu void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); 14011025Snilay@cs.wisc.edu void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, 14110524Snilay@cs.wisc.edu const DataBlock &block); 14211025Snilay@cs.wisc.edu void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, 14310524Snilay@cs.wisc.edu const DataBlock &block, int size); 14410524Snilay@cs.wisc.edu void recvTimingResp(PacketPtr pkt); 14512395Sswapnilster@gmail.com Tick recvAtomic(PacketPtr pkt); 14610524Snilay@cs.wisc.edu 14712065Snikos.nikoleris@arm.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 14812065Snikos.nikoleris@arm.com 1499496Snilay@cs.wisc.edu public: 1509496Snilay@cs.wisc.edu MachineID getMachineID() const { return m_machineID; } 1519496Snilay@cs.wisc.edu 15210012Snilay@cs.wisc.edu Stats::Histogram& getDelayHist() { return m_delayHistogram; } 15310012Snilay@cs.wisc.edu Stats::Histogram& getDelayVCHist(uint32_t index) 15410012Snilay@cs.wisc.edu { return *(m_delayVCHistogram[index]); } 1559497Snilay@cs.wisc.edu 15612065Snikos.nikoleris@arm.com /** 15712065Snikos.nikoleris@arm.com * Map an address to the correct MachineID 15812065Snikos.nikoleris@arm.com * 15912065Snikos.nikoleris@arm.com * This function querries the network for the NodeID of the 16012065Snikos.nikoleris@arm.com * destination for a given request using its address and the type 16112065Snikos.nikoleris@arm.com * of the destination. For example for a request with a given 16212065Snikos.nikoleris@arm.com * address to a directory it will return the MachineID of the 16312065Snikos.nikoleris@arm.com * authorative directory. 16412065Snikos.nikoleris@arm.com * 16512065Snikos.nikoleris@arm.com * @param the destination address 16612065Snikos.nikoleris@arm.com * @param the type of the destination 16712065Snikos.nikoleris@arm.com * @return the MachineID of the destination 16812065Snikos.nikoleris@arm.com */ 16912065Snikos.nikoleris@arm.com MachineID mapAddressToMachine(Addr addr, MachineType mtype) const; 17012065Snikos.nikoleris@arm.com 1719496Snilay@cs.wisc.edu protected: 1729496Snilay@cs.wisc.edu //! Profiles original cache requests including PUTs 1739496Snilay@cs.wisc.edu void profileRequest(const std::string &request); 1749497Snilay@cs.wisc.edu //! Profiles the delay associated with messages. 1759507Snilay@cs.wisc.edu void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 1769496Snilay@cs.wisc.edu 17711025Snilay@cs.wisc.edu void stallBuffer(MessageBuffer* buf, Addr addr); 17811025Snilay@cs.wisc.edu void wakeUpBuffers(Addr addr); 17911025Snilay@cs.wisc.edu void wakeUpAllBuffers(Addr addr); 1809596Snilay@cs.wisc.edu void wakeUpAllBuffers(); 1819596Snilay@cs.wisc.edu 1829364Snilay@cs.wisc.edu protected: 18311121Snilay@cs.wisc.edu const NodeID m_version; 18410005Snilay@cs.wisc.edu MachineID m_machineID; 18511121Snilay@cs.wisc.edu const NodeID m_clusterID; 18610005Snilay@cs.wisc.edu 18710524Snilay@cs.wisc.edu // MasterID used by some components of gem5. 18811121Snilay@cs.wisc.edu const MasterID m_masterId; 18910524Snilay@cs.wisc.edu 19011121Snilay@cs.wisc.edu Network *m_net_ptr; 1919364Snilay@cs.wisc.edu bool m_is_blocking; 19211025Snilay@cs.wisc.edu std::map<Addr, MessageBuffer*> m_block_map; 19310087Snilay@cs.wisc.edu 1949364Snilay@cs.wisc.edu typedef std::vector<MessageBuffer*> MsgVecType; 19510977Sdavid.hashe@amd.com typedef std::set<MessageBuffer*> MsgBufType; 19611025Snilay@cs.wisc.edu typedef std::map<Addr, MsgVecType* > WaitingBufType; 1979364Snilay@cs.wisc.edu WaitingBufType m_waiting_buffers; 19810087Snilay@cs.wisc.edu 1999996Snilay@cs.wisc.edu unsigned int m_in_ports; 2009996Snilay@cs.wisc.edu unsigned int m_cur_in_port; 20111121Snilay@cs.wisc.edu const int m_number_of_TBEs; 20211121Snilay@cs.wisc.edu const int m_transitions_per_cycle; 20311121Snilay@cs.wisc.edu const unsigned int m_buffer_size; 20410005Snilay@cs.wisc.edu Cycles m_recycle_latency; 20513974Stiago.muck@arm.com const Cycles m_mandatory_queue_latency; 2069496Snilay@cs.wisc.edu 2079496Snilay@cs.wisc.edu //! Counter for the number of cycles when the transitions carried out 2089496Snilay@cs.wisc.edu //! were equal to the maximum allowed 20910012Snilay@cs.wisc.edu Stats::Scalar m_fully_busy_cycles; 2109497Snilay@cs.wisc.edu 2119497Snilay@cs.wisc.edu //! Histogram for profiling delay for the messages this controller 2129497Snilay@cs.wisc.edu //! cares for 21310012Snilay@cs.wisc.edu Stats::Histogram m_delayHistogram; 21410012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_delayVCHistogram; 2159745Snilay@cs.wisc.edu 2169745Snilay@cs.wisc.edu //! Callback class used for collating statistics from all the 2179745Snilay@cs.wisc.edu //! controller of this type. 2189745Snilay@cs.wisc.edu class StatsCallback : public Callback 2199745Snilay@cs.wisc.edu { 2209745Snilay@cs.wisc.edu private: 2219745Snilay@cs.wisc.edu AbstractController *ctr; 2229745Snilay@cs.wisc.edu 2239745Snilay@cs.wisc.edu public: 2249745Snilay@cs.wisc.edu virtual ~StatsCallback() {} 22510012Snilay@cs.wisc.edu StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 2269745Snilay@cs.wisc.edu void process() {ctr->collateStats();} 2279745Snilay@cs.wisc.edu }; 22810524Snilay@cs.wisc.edu 22910524Snilay@cs.wisc.edu /** 23010524Snilay@cs.wisc.edu * Port that forwards requests and receives responses from the 23110524Snilay@cs.wisc.edu * memory controller. It has a queue of packets not yet sent. 23210524Snilay@cs.wisc.edu */ 23310524Snilay@cs.wisc.edu class MemoryPort : public QueuedMasterPort 23410524Snilay@cs.wisc.edu { 23510524Snilay@cs.wisc.edu private: 23610713Sandreas.hansson@arm.com // Packet queues used to store outgoing requests and snoop responses. 23710713Sandreas.hansson@arm.com ReqPacketQueue reqQueue; 23810713Sandreas.hansson@arm.com SnoopRespPacketQueue snoopRespQueue; 23910524Snilay@cs.wisc.edu 24010524Snilay@cs.wisc.edu // Controller that operates this port. 24110524Snilay@cs.wisc.edu AbstractController *controller; 24210524Snilay@cs.wisc.edu 24310524Snilay@cs.wisc.edu public: 24410524Snilay@cs.wisc.edu MemoryPort(const std::string &_name, AbstractController *_controller, 24510524Snilay@cs.wisc.edu const std::string &_label); 24610524Snilay@cs.wisc.edu 24710524Snilay@cs.wisc.edu // Function for receiving a timing response from the peer port. 24810524Snilay@cs.wisc.edu // Currently the pkt is handed to the coherence controller 24910524Snilay@cs.wisc.edu // associated with this port. 25010524Snilay@cs.wisc.edu bool recvTimingResp(PacketPtr pkt); 25110524Snilay@cs.wisc.edu }; 25210524Snilay@cs.wisc.edu 25310524Snilay@cs.wisc.edu /* Master port to the memory controller. */ 25410524Snilay@cs.wisc.edu MemoryPort memoryPort; 25510524Snilay@cs.wisc.edu 25610524Snilay@cs.wisc.edu // State that is stored in packets sent to the memory controller. 25710524Snilay@cs.wisc.edu struct SenderState : public Packet::SenderState 25810524Snilay@cs.wisc.edu { 25910524Snilay@cs.wisc.edu // Id of the machine from which the request originated. 26010524Snilay@cs.wisc.edu MachineID id; 26110524Snilay@cs.wisc.edu 26210524Snilay@cs.wisc.edu SenderState(MachineID _id) : id(_id) 26310524Snilay@cs.wisc.edu {} 26410524Snilay@cs.wisc.edu }; 26512065Snikos.nikoleris@arm.com 26612065Snikos.nikoleris@arm.com private: 26712065Snikos.nikoleris@arm.com /** The address range to which the controller responds on the CPU side. */ 26812065Snikos.nikoleris@arm.com const AddrRangeList addrRanges; 2696285Snate@binkert.org}; 2706285Snate@binkert.org 2717039Snate@binkert.org#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 272