AbstractController.hh revision 11021
12SN/A/* 21762SN/A * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 302SN/A#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 312SN/A 322SN/A#include <exception> 332SN/A#include <iostream> 342SN/A#include <string> 352SN/A 362SN/A#include "base/callback.hh" 372432SN/A#include "mem/protocol/AccessPermission.hh" 381147SN/A#include "mem/ruby/common/Address.hh" 392090SN/A#include "mem/ruby/common/Consumer.hh" 401147SN/A#include "mem/ruby/common/DataBlock.hh" 412517SN/A#include "mem/ruby/common/Histogram.hh" 4256SN/A#include "mem/ruby/common/MachineID.hh" 432SN/A#include "mem/ruby/network/MessageBuffer.hh" 442680Sktlim@umich.edu#include "mem/ruby/network/Network.hh" 452SN/A#include "mem/ruby/system/CacheRecorder.hh" 46674SN/A#include "mem/packet.hh" 472SN/A#include "mem/qport.hh" 482SN/A#include "params/RubyController.hh" 492SN/A#include "mem/mem_object.hh" 502SN/A 512SN/Aclass Network; 522SN/A 532SN/A// used to communicate that an in_port peeked the wrong message type 542SN/Aclass RejectException: public std::exception 552SN/A{ 562SN/A virtual const char* what() const throw() 572SN/A { return "Port rejected message based on type"; } 582SN/A}; 592SN/A 60674SN/Aclass AbstractController : public MemObject, public Consumer 61674SN/A{ 622SN/A public: 632SN/A typedef RubyControllerParams Params; 642SN/A AbstractController(const Params *p); 65555SN/A void init(); 662SN/A const Params *params() const { return (const Params *)_params; } 672SN/A 682SN/A const NodeID getVersion() const { return m_machineID.getNum(); } 692SN/A const MachineType getType() const { return m_machineID.getType(); } 702SN/A 712SN/A void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 722SN/A 732SN/A // return instance name 742SN/A void blockOnQueue(Address, MessageBuffer*); 751147SN/A void unblock(Address); 761147SN/A 772SN/A virtual MessageBuffer* getMandatoryQueue() const = 0; 782SN/A virtual MessageBuffer* getMemoryQueue() const = 0; 792532SN/A virtual AccessPermission getAccessPermission(const Address& addr) = 0; 802SN/A 812SN/A virtual void print(std::ostream & out) const = 0; 82217SN/A virtual void wakeup() = 0; 83237SN/A virtual void resetStats() = 0; 842SN/A virtual void regStats(); 852SN/A 86674SN/A virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 872SN/A virtual Sequencer* getSequencer() const = 0; 882SN/A 89729SN/A //! These functions are used by ruby system to read/write the data blocks 90729SN/A //! that exist with in the controller. 91729SN/A virtual void functionalRead(const Address &addr, PacketPtr) = 0; 92729SN/A void functionalMemoryRead(PacketPtr); 932SN/A //! The return value indicates the number of messages written with the 942SN/A //! data from the packet. 95674SN/A virtual int functionalWriteBuffers(PacketPtr&) = 0; 962SN/A virtual int functionalWrite(const Address &addr, PacketPtr) = 0; 972SN/A int functionalMemoryWrite(PacketPtr); 982680Sktlim@umich.edu 992SN/A //! Function for enqueuing a prefetch request 1002SN/A virtual void enqueuePrefetch(const Address&, const RubyRequestType&) 101674SN/A { fatal("Prefetches not implemented!");} 1022SN/A 1032SN/A //! Function for collating statistics from all the controllers of this 104729SN/A //! particular type. This function should only be called from the 105729SN/A //! version 0 of this controller type. 106729SN/A virtual void collateStats() 107729SN/A {fatal("collateStats() should be overridden!");} 108729SN/A 109729SN/A //! Initialize the message buffers. 110729SN/A virtual void initNetQueues() = 0; 111729SN/A 112729SN/A /** A function used to return the port associated with this bus object. */ 113729SN/A BaseMasterPort& getMasterPort(const std::string& if_name, 114729SN/A PortID idx = InvalidPortID); 115729SN/A 1162SN/A void queueMemoryRead(const MachineID &id, Address addr, Cycles latency); 1172SN/A void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency, 118674SN/A const DataBlock &block); 1192SN/A void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency, 1202SN/A const DataBlock &block, int size); 1212680Sktlim@umich.edu void recvTimingResp(PacketPtr pkt); 1222SN/A 1232SN/A public: 1242SN/A MachineID getMachineID() const { return m_machineID; } 125 126 Stats::Histogram& getDelayHist() { return m_delayHistogram; } 127 Stats::Histogram& getDelayVCHist(uint32_t index) 128 { return *(m_delayVCHistogram[index]); } 129 130 protected: 131 //! Profiles original cache requests including PUTs 132 void profileRequest(const std::string &request); 133 //! Profiles the delay associated with messages. 134 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 135 136 void stallBuffer(MessageBuffer* buf, Address addr); 137 void wakeUpBuffers(Address addr); 138 void wakeUpAllBuffers(Address addr); 139 void wakeUpAllBuffers(); 140 141 protected: 142 NodeID m_version; 143 MachineID m_machineID; 144 NodeID m_clusterID; 145 146 // MasterID used by some components of gem5. 147 MasterID m_masterId; 148 149 Network* m_net_ptr; 150 bool m_is_blocking; 151 std::map<Address, MessageBuffer*> m_block_map; 152 153 typedef std::vector<MessageBuffer*> MsgVecType; 154 typedef std::set<MessageBuffer*> MsgBufType; 155 typedef std::map< Address, MsgVecType* > WaitingBufType; 156 WaitingBufType m_waiting_buffers; 157 158 unsigned int m_in_ports; 159 unsigned int m_cur_in_port; 160 int m_number_of_TBEs; 161 int m_transitions_per_cycle; 162 unsigned int m_buffer_size; 163 Cycles m_recycle_latency; 164 165 //! Counter for the number of cycles when the transitions carried out 166 //! were equal to the maximum allowed 167 Stats::Scalar m_fully_busy_cycles; 168 169 //! Histogram for profiling delay for the messages this controller 170 //! cares for 171 Stats::Histogram m_delayHistogram; 172 std::vector<Stats::Histogram *> m_delayVCHistogram; 173 174 //! Callback class used for collating statistics from all the 175 //! controller of this type. 176 class StatsCallback : public Callback 177 { 178 private: 179 AbstractController *ctr; 180 181 public: 182 virtual ~StatsCallback() {} 183 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 184 void process() {ctr->collateStats();} 185 }; 186 187 /** 188 * Port that forwards requests and receives responses from the 189 * memory controller. It has a queue of packets not yet sent. 190 */ 191 class MemoryPort : public QueuedMasterPort 192 { 193 private: 194 // Packet queues used to store outgoing requests and snoop responses. 195 ReqPacketQueue reqQueue; 196 SnoopRespPacketQueue snoopRespQueue; 197 198 // Controller that operates this port. 199 AbstractController *controller; 200 201 public: 202 MemoryPort(const std::string &_name, AbstractController *_controller, 203 const std::string &_label); 204 205 // Function for receiving a timing response from the peer port. 206 // Currently the pkt is handed to the coherence controller 207 // associated with this port. 208 bool recvTimingResp(PacketPtr pkt); 209 }; 210 211 /* Master port to the memory controller. */ 212 MemoryPort memoryPort; 213 214 // State that is stored in packets sent to the memory controller. 215 struct SenderState : public Packet::SenderState 216 { 217 // Id of the machine from which the request originated. 218 MachineID id; 219 220 SenderState(MachineID _id) : id(_id) 221 {} 222 }; 223}; 224 225#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 226