RubySlicc_Types.sm revision 14262:991410960fdb 
1/*
2 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30// External Types
31
32//
33// **PLEASE NOTE!**  When adding objects to this file you must also add a line
34// in the src/mem/ruby/SConscript file.  Otherwise the external object's .hh
35// file will not be copied to the protocol directory and you will encounter a
36// undefined declaration error.
37//
38
39external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
40external_type(OutPort, primitive="yes");
41external_type(Scalar, primitive="yes");
42
43structure(InPort, external = "yes", primitive="yes") {
44  bool isReady(Tick current_time);
45  Tick dequeue(Tick current_time);
46  void recycle(Tick current_time, Tick recycle_latency);
47  bool isEmpty();
48  bool isStallMapEmpty();
49  int getStallMapSize();
50}
51
52external_type(NodeID, default="0", primitive="yes");
53external_type(MachineID);
54
55structure (Set, external = "yes", non_obj="yes") {
56  void setSize(int);
57  void add(NodeID);
58  void addSet(Set);
59  void remove(NodeID);
60  void removeSet(Set);
61  void broadcast();
62  void addRandom();
63  void clear();
64  int count();
65  bool isElement(NodeID);
66  bool isEqual(Set);
67  bool isSuperset(Set);
68  bool intersectionIsEmpty(Set);
69  NodeID smallestElement();
70}
71
72structure (NetDest, external = "yes", non_obj="yes") {
73  void setSize(int);
74  void setSize(int, int);
75  void add(NodeID);
76  void add(MachineID);
77  void addSet(Set);
78  void addNetDest(NetDest);
79  void setNetDest(MachineType, Set);
80  void remove(NodeID);
81  void remove(MachineID);
82  void removeSet(Set);
83  void removeNetDest(NetDest);
84  void broadcast();
85  void broadcast(MachineType);
86  void addRandom();
87  void clear();
88  Set toSet();
89  int count();
90  bool isElement(NodeID);
91  bool isElement(MachineID);
92  bool isSuperset(Set);
93  bool isSuperset(NetDest);
94  bool isEmpty();
95  bool intersectionIsEmpty(Set);
96  bool intersectionIsEmpty(NetDest);
97  MachineID smallestElement(MachineType);
98  NetDest OR(NetDest);
99  NetDest AND(NetDest);
100}
101
102structure (Sequencer, external = "yes") {
103  void readCallback(Addr, DataBlock);
104  void readCallback(Addr, DataBlock, bool);
105  void readCallback(Addr, DataBlock, bool, MachineType);
106  void readCallback(Addr, DataBlock, bool, MachineType,
107                    Cycles, Cycles, Cycles);
108
109  void writeCallback(Addr, DataBlock);
110  void writeCallback(Addr, DataBlock, bool);
111  void writeCallback(Addr, DataBlock, bool, MachineType);
112  void writeCallback(Addr, DataBlock, bool, MachineType,
113                     Cycles, Cycles, Cycles);
114
115  void checkCoherence(Addr);
116  void evictionCallback(Addr);
117  void recordRequestType(SequencerRequestType);
118  bool checkResourceAvailable(CacheResourceType, Addr);
119  void invalidateSC(Addr);
120}
121
122structure (GPUCoalescer, external = "yes") {
123  void readCallback(Addr, DataBlock);
124  void readCallback(Addr, MachineType, DataBlock);
125  void readCallback(Addr, MachineType, DataBlock,
126                    Cycles, Cycles, Cycles);
127  void readCallback(Addr, MachineType, DataBlock,
128                    Cycles, Cycles, Cycles, bool);
129  void writeCallback(Addr, DataBlock);
130  void writeCallback(Addr, MachineType, DataBlock);
131  void writeCallback(Addr, MachineType, DataBlock,
132                     Cycles, Cycles, Cycles);
133  void writeCallback(Addr, MachineType, DataBlock,
134                     Cycles, Cycles, Cycles, bool);
135  void checkCoherence(Addr);
136  void evictionCallback(Addr);
137  void recordCPReadCallBack(MachineID, MachineID);
138  void recordCPWriteCallBack(MachineID, MachineID);
139}
140
141structure (VIPERCoalescer, external = "yes") {
142  void readCallback(Addr, DataBlock);
143  void readCallback(Addr, MachineType, DataBlock);
144  void readCallback(Addr, MachineType, DataBlock,
145                    Cycles, Cycles, Cycles);
146  void readCallback(Addr, MachineType, DataBlock,
147                    Cycles, Cycles, Cycles, bool);
148  void writeCallback(Addr, DataBlock);
149  void writeCallback(Addr, MachineType, DataBlock);
150  void writeCallback(Addr, MachineType, DataBlock,
151                     Cycles, Cycles, Cycles);
152  void writeCallback(Addr, MachineType, DataBlock,
153                     Cycles, Cycles, Cycles, bool);
154  void invCallback(Addr);
155  void wbCallback(Addr);
156  void checkCoherence(Addr);
157  void evictionCallback(Addr);
158}
159
160structure(RubyRequest, desc="...", interface="Message", external="yes") {
161  Addr LineAddress,       desc="Line address for this request";
162  Addr PhysicalAddress,   desc="Physical address for this request";
163  RubyRequestType Type,      desc="Type of request (LD, ST, etc)";
164  Addr ProgramCounter,    desc="Program counter of the instruction that caused the miss";
165  RubyAccessMode AccessMode, desc="user/supervisor access type";
166  int Size,                  desc="size in bytes of access";
167  PrefetchBit Prefetch,      desc="Is this a prefetch request";
168  int contextId,             desc="this goes away but must be replace with Nilay";
169  WriteMask writeMask,       desc="Writethrough mask";
170  DataBlock WTData,          desc="Writethrough data block";
171  int wfid,                  desc="Writethrough wavefront";
172  HSAScope scope,            desc="HSA scope";
173  HSASegment segment,        desc="HSA segment";
174  PacketPtr pkt,             desc="Packet associated with this request";
175}
176
177structure(AbstractEntry, primitive="yes", external = "yes") {
178  void changePermission(AccessPermission);
179}
180
181structure (DirectoryMemory, external = "yes") {
182  AbstractEntry allocate(Addr, AbstractEntry);
183  AbstractEntry lookup(Addr);
184  bool isPresent(Addr);
185  void invalidateBlock(Addr);
186  void recordRequestType(DirectoryRequestType);
187}
188
189structure(AbstractCacheEntry, primitive="yes", external = "yes") {
190  void changePermission(AccessPermission);
191}
192
193structure (CacheMemory, external = "yes") {
194  bool cacheAvail(Addr);
195  Addr cacheProbe(Addr);
196  AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
197  AbstractCacheEntry allocate(Addr, AbstractCacheEntry, bool);
198  void allocateVoid(Addr, AbstractCacheEntry);
199  void deallocate(Addr);
200  AbstractCacheEntry lookup(Addr);
201  bool isTagPresent(Addr);
202  Cycles getTagLatency();
203  Cycles getDataLatency();
204  void setMRU(Addr);
205  void setMRU(Addr, int);
206  void setMRU(AbstractCacheEntry);
207  void recordRequestType(CacheRequestType, Addr);
208  bool checkResourceAvailable(CacheResourceType, Addr);
209
210  int getCacheSize();
211  int getNumBlocks();
212  Addr getAddressAtIdx(int);
213
214  Scalar demand_misses;
215  Scalar demand_hits;
216}
217
218structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
219
220}
221
222structure (DMASequencer, external = "yes") {
223  void ackCallback(Addr);
224  void dataCallback(DataBlock,Addr);
225  void recordRequestType(CacheRequestType);
226}
227
228structure (TimerTable, inport="yes", external = "yes") {
229  bool isReady(Tick);
230  Addr nextAddress();
231  void set(Addr, Tick);
232  void unset(Addr);
233  bool isSet(Addr);
234}
235
236structure (Prefetcher, external = "yes") {
237    void observeMiss(Addr, RubyRequestType);
238    void observePfHit(Addr);
239    void observePfMiss(Addr);
240}
241