MESI_Two_Level-dma.sm revision 14184:11ac1337c5e2 
1/*
2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30machine(MachineType:DMA, "DMA Controller")
31: DMASequencer * dma_sequencer;
32  Cycles request_latency := 6;
33
34  MessageBuffer * responseFromDir, network="From", virtual_network="1",
35        vnet_type="response";
36  MessageBuffer * requestToDir, network="To", virtual_network="0",
37        vnet_type="request";
38  MessageBuffer * mandatoryQueue;
39{
40  state_declaration(State, desc="DMA states", default="DMA_State_READY") {
41    READY, AccessPermission:Invalid, desc="Ready to accept a new request";
42    BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
43    BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
44  }
45
46  enumeration(Event, desc="DMA events") {
47    ReadRequest,  desc="A new read request";
48    WriteRequest, desc="A new write request";
49    Data,         desc="Data from a DMA memory read";
50    Ack,          desc="DMA write to memory completed";
51  }
52
53  structure(TBE, desc="...") {
54    State TBEState,    desc="Transient state";
55    DataBlock DataBlk, desc="Data";
56  }
57
58  structure(TBETable, external = "yes") {
59    TBE lookup(Addr);
60    void allocate(Addr);
61    void deallocate(Addr);
62    bool isPresent(Addr);
63  }
64
65  void set_tbe(TBE b);
66  void unset_tbe();
67  void wakeUpAllBuffers();
68
69  TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
70
71  Tick clockEdge();
72  MachineID mapAddressToMachine(Addr addr, MachineType mtype);
73
74  State getState(TBE tbe, Addr addr) {
75    if (is_valid(tbe)) {
76        return tbe.TBEState;
77    } else {
78        return State:READY;
79    }
80  }
81
82  void setState(TBE tbe, Addr addr, State state) {
83    if (is_valid(tbe)) {
84        tbe.TBEState := state;
85    }
86  }
87
88  AccessPermission getAccessPermission(Addr addr) {
89    return AccessPermission:NotPresent;
90  }
91
92  void setAccessPermission(Addr addr, State state) {
93  }
94
95  void functionalRead(Addr addr, Packet *pkt) {
96    error("DMA does not support functional read.");
97  }
98
99  int functionalWrite(Addr addr, Packet *pkt) {
100    error("DMA does not support functional write.");
101  }
102
103  out_port(requestToDir_out, RequestMsg, requestToDir, desc="...");
104
105  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
106    if (dmaRequestQueue_in.isReady(clockEdge())) {
107      peek(dmaRequestQueue_in, SequencerMsg) {
108        if (in_msg.Type == SequencerRequestType:LD ) {
109          trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
110        } else if (in_msg.Type == SequencerRequestType:ST) {
111          trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
112        } else {
113          error("Invalid request type");
114        }
115      }
116    }
117  }
118
119  in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
120    if (dmaResponseQueue_in.isReady(clockEdge())) {
121      peek( dmaResponseQueue_in, ResponseMsg) {
122        if (in_msg.Type == CoherenceResponseType:ACK) {
123          trigger(Event:Ack, makeLineAddress(in_msg.addr),
124                  TBEs[makeLineAddress(in_msg.addr)]);
125        } else if (in_msg.Type == CoherenceResponseType:DATA) {
126          trigger(Event:Data, makeLineAddress(in_msg.addr),
127                  TBEs[makeLineAddress(in_msg.addr)]);
128        } else {
129          error("Invalid response type");
130        }
131      }
132    }
133  }
134
135  action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
136    peek(dmaRequestQueue_in, SequencerMsg) {
137      enqueue(requestToDir_out, RequestMsg, request_latency) {
138        out_msg.addr := in_msg.PhysicalAddress;
139        out_msg.Type := CoherenceRequestType:DMA_READ;
140        out_msg.Requestor := machineID;
141        out_msg.DataBlk := in_msg.DataBlk;
142        out_msg.Len := in_msg.Len;
143        out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
144        out_msg.MessageSize := MessageSizeType:Writeback_Control;
145      }
146    }
147  }
148
149  action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
150    peek(dmaRequestQueue_in, SequencerMsg) {
151      enqueue(requestToDir_out, RequestMsg, request_latency) {
152          out_msg.addr := in_msg.PhysicalAddress;
153          out_msg.Type := CoherenceRequestType:DMA_WRITE;
154          out_msg.Requestor := machineID;
155          out_msg.DataBlk := in_msg.DataBlk;
156          out_msg.Len := in_msg.Len;
157          out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
158          out_msg.MessageSize := MessageSizeType:Writeback_Control;
159        }
160      }
161  }
162
163  action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
164    dma_sequencer.ackCallback(address);
165  }
166
167  action(d_dataCallback, "d", desc="Write data to dma sequencer") {
168    dma_sequencer.dataCallback(tbe.DataBlk, address);
169  }
170
171  action(t_updateTBEData, "t", desc="Update TBE Data") {
172    assert(is_valid(tbe));
173    peek( dmaResponseQueue_in, ResponseMsg) {
174        tbe.DataBlk := in_msg.DataBlk;
175    }
176  }
177
178  action(v_allocateTBE, "v", desc="Allocate TBE entry") {
179    TBEs.allocate(address);
180    set_tbe(TBEs[address]);
181  }
182
183  action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
184    TBEs.deallocate(address);
185    unset_tbe();
186  }
187
188  action(p_popRequestQueue, "p", desc="Pop request queue") {
189    dmaRequestQueue_in.dequeue(clockEdge());
190  }
191
192  action(p_popResponseQueue, "\p", desc="Pop request queue") {
193    dmaResponseQueue_in.dequeue(clockEdge());
194  }
195
196  action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
197    stall_and_wait(dmaRequestQueue_in, address);
198  }
199
200  action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
201    wakeUpAllBuffers();
202  }
203
204  transition(READY, ReadRequest, BUSY_RD) {
205    v_allocateTBE;
206    s_sendReadRequest;
207    p_popRequestQueue;
208  }
209
210  transition(READY, WriteRequest, BUSY_WR) {
211    v_allocateTBE;
212    s_sendWriteRequest;
213    p_popRequestQueue;
214  }
215
216  transition(BUSY_RD, Data, READY) {
217    t_updateTBEData;
218    d_dataCallback;
219    w_deallocateTBE;
220    p_popResponseQueue;
221    wkad_wakeUpAllDependents;
222  }
223
224  transition(BUSY_WR, Ack, READY) {
225    a_ackCallback;
226    w_deallocateTBE;
227    p_popResponseQueue;
228    wkad_wakeUpAllDependents;
229  }
230
231  transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
232     zz_stallAndWaitRequestQueue;
233  }
234
235}
236