MESI_Three_Level-msg.sm revision 14184:11ac1337c5e2 
1/*
2 * Copyright (c) 2013 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Various class of messages that can be exchanged between the L0 and the L1
30// controllers.
31enumeration(CoherenceClass, desc="...") {
32  GETX,      desc="Get eXclusive";
33  UPGRADE,   desc="UPGRADE to exclusive";
34  GETS,      desc="Get Shared";
35  GET_INSTR, desc="Get Instruction";
36  INV,       desc="INValidate";
37  PUTX,      desc="Replacement message";
38
39  WB_ACK,    desc="Writeback ack";
40
41  // Request types for sending data and acks from L0 to L1 cache
42  // when an invalidation message is received.
43  INV_DATA;
44  INV_ACK;
45
46  DATA, desc="Data block for L1 cache in S state";
47  DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
48  ACK, desc="Generic invalidate ack";
49
50  // This is a special case in which the L1 cache lost permissions to the
51  // shared block before it got the data. So the L0 cache can use the data
52  // but not store it.
53  STALE_DATA;
54}
55
56// Class for messages sent between the L0 and the L1 controllers.
57structure(CoherenceMsg, desc="...", interface="Message") {
58  Addr addr,              desc="Physical address of the cache block";
59  CoherenceClass Class,         desc="Type of message (GetS, GetX, PutX, etc)";
60  RubyAccessMode AccessMode,    desc="user/supervisor access type";
61  MachineID Sender,             desc="What component sent this message";
62  MachineID Dest,        desc="What machine receives this message";
63  MessageSizeType MessageSize,  desc="size category of the message";
64  DataBlock DataBlk,            desc="Data for the cache line (if PUTX)";
65  bool Dirty, default="false",  desc="Dirty bit";
66
67  bool functionalRead(Packet *pkt) {
68    // Only PUTX messages contains the data block
69    if (Class == CoherenceClass:PUTX) {
70        return testAndRead(addr, DataBlk, pkt);
71    }
72
73    return false;
74  }
75
76  bool functionalWrite(Packet *pkt) {
77    // No check on message type required since the protocol should
78    // read data from those messages that contain the block
79    return testAndWrite(addr, DataBlk, pkt);
80  }
81}
82