Profiler.hh revision 6889:323cd43a3c46
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44 45/* 46 * Profiler.hh 47 * 48 * Description: 49 * 50 * $Id$ 51 * 52 */ 53 54#ifndef PROFILER_H 55#define PROFILER_H 56 57#include "mem/ruby/libruby.hh" 58 59#include "mem/ruby/common/Global.hh" 60#include "mem/protocol/GenericMachineType.hh" 61#include "mem/ruby/common/Histogram.hh" 62#include "mem/ruby/common/Consumer.hh" 63#include "mem/protocol/AccessModeType.hh" 64#include "mem/protocol/AccessType.hh" 65#include "mem/ruby/system/NodeID.hh" 66#include "mem/ruby/system/MachineID.hh" 67#include "mem/protocol/PrefetchBit.hh" 68#include "mem/ruby/common/Address.hh" 69#include "mem/ruby/common/Set.hh" 70#include "mem/protocol/CacheRequestType.hh" 71#include "mem/protocol/GenericRequestType.hh" 72#include "mem/ruby/system/MemoryControl.hh" 73 74#include "params/RubyProfiler.hh" 75#include "sim/sim_object.hh" 76 77class CacheMsg; 78class AddressProfiler; 79 80template <class KEY_TYPE, class VALUE_TYPE> class Map; 81 82struct memory_control_profiler { 83 uint64 m_memReq; 84 uint64 m_memBankBusy; 85 uint64 m_memBusBusy; 86 uint64 m_memTfawBusy; 87 uint64 m_memReadWriteBusy; 88 uint64 m_memDataBusBusy; 89 uint64 m_memRefresh; 90 uint64 m_memRead; 91 uint64 m_memWrite; 92 uint64 m_memWaitCycles; 93 uint64 m_memInputQ; 94 uint64 m_memBankQ; 95 uint64 m_memArbWait; 96 uint64 m_memRandBusy; 97 uint64 m_memNotOld; 98 Vector<uint64> m_memBankCount; 99 int m_banks_per_rank; 100 int m_ranks_per_dimm; 101 int m_dimms_per_channel; 102}; 103 104 105class Profiler : public SimObject, public Consumer { 106public: 107 // Constructors 108 typedef RubyProfilerParams Params; 109 Profiler(const Params *); 110 111 // Destructor 112 ~Profiler(); 113 114 // Public Methods 115 void wakeup(); 116 117 void setPeriodicStatsFile(const string& filename); 118 void setPeriodicStatsInterval(integer_t period); 119 120 void printStats(ostream& out, bool short_stats=false); 121 void printShortStats(ostream& out) { printStats(out, true); } 122 void printTraceStats(ostream& out) const; 123 void clearStats(); 124 void printConfig(ostream& out) const; 125 void printResourceUsage(ostream& out) const; 126 127 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 128 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } 129 130 void addAddressTraceSample(const CacheMsg& msg, NodeID id); 131 132 void profileRequest(const string& requestStr); 133 void profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner); 134 135 void profileMulticastRetry(const Address& addr, int count); 136 137 void profileFilterAction(int action); 138 139 void profileConflictingRequests(const Address& addr); 140 void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); } 141 void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); } 142 void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); } 143 144 void recordPrediction(bool wasGood, bool wasPredicted); 145 146 void startTransaction(int cpu); 147 void endTransaction(int cpu); 148 void profilePFWait(Time waitTime); 149 150 void controllerBusy(MachineID machID); 151 void bankBusy(); 152 void missLatency(Time t, RubyRequestType type); 153 void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach); 154 void sequencerRequests(int num) { m_sequencer_requests.add(num); } 155 156 void profileTransition(const string& component, NodeID version, Address addr, 157 const string& state, const string& event, 158 const string& next_state, const string& note); 159 void profileMsgDelay(int virtualNetwork, int delayCycles); 160 161 void print(ostream& out) const; 162 163 int64 getTotalTransactionsExecuted() const; 164 165 void rubyWatch(int proc); 166 bool watchAddress(Address addr); 167 168 // return Ruby's start time 169 Time getRubyStartTime(){ 170 return m_ruby_start; 171 } 172 173 // added for MemoryControl: 174 void profileMemReq(int mem_cntrl, int bank); 175 void profileMemBankBusy(int mem_cntrl); 176 void profileMemBusBusy(int mem_cntrl); 177 void profileMemTfawBusy(int mem_cntrl); 178 void profileMemReadWriteBusy(int mem_cntrl); 179 void profileMemDataBusBusy(int mem_cntrl); 180 void profileMemRefresh(int mem_cntrl); 181 void profileMemRead(int mem_cntrl); 182 void profileMemWrite(int mem_cntrl); 183 void profileMemWaitCycles(int mem_cntrl, int cycles); 184 void profileMemInputQ(int mem_cntrl, int cycles); 185 void profileMemBankQ(int mem_cntrl, int cycles); 186 void profileMemArbWait(int mem_cntrl, int cycles); 187 void profileMemRandBusy(int mem_cntrl); 188 void profileMemNotOld(int mem_cntrl); 189 //added by SS 190 bool getHotLines() { return m_hot_lines; } 191 bool getAllInstructions() { return m_all_instructions; } 192 193private: 194 //added by SS 195 vector<string> m_memory_control_names; 196 197 // Private copy constructor and assignment operator 198 Profiler(const Profiler& obj); 199 Profiler& operator=(const Profiler& obj); 200 201 // Data Members (m_ prefix) 202 AddressProfiler* m_address_profiler_ptr; 203 AddressProfiler* m_inst_profiler_ptr; 204 205 Vector<int64> m_instructions_executed_at_start; 206 Vector<int64> m_cycles_executed_at_start; 207 208 ostream* m_periodic_output_file_ptr; 209 integer_t m_stats_period; 210 211 Time m_ruby_start; 212 time_t m_real_time_start_time; 213 214 Vector<integer_t> m_perProcTotalMisses; 215 Vector<integer_t> m_perProcUserMisses; 216 Vector<integer_t> m_perProcSupervisorMisses; 217 Vector<integer_t> m_perProcStartTransaction; 218 Vector<integer_t> m_perProcEndTransaction; 219 Vector < Vector < integer_t > > m_busyControllerCount; 220 integer_t m_busyBankCount; 221 Histogram m_multicast_retry_histogram; 222 223 Histogram m_filter_action_histogram; 224 Histogram m_tbeProfile; 225 226 Histogram m_sequencer_requests; 227 Histogram m_read_sharing_histogram; 228 Histogram m_write_sharing_histogram; 229 Histogram m_all_sharing_histogram; 230 int64 m_cache_to_cache; 231 int64 m_memory_to_cache; 232 233 Histogram m_prefetchWaitHistogram; 234 235 Vector<Histogram> m_missLatencyHistograms; 236 Vector<Histogram> m_machLatencyHistograms; 237 Histogram m_allMissLatencyHistogram; 238 239 Histogram m_allSWPrefetchLatencyHistogram; 240 Histogram m_SWPrefetchL2MissLatencyHistogram; 241 Vector<Histogram> m_SWPrefetchLatencyHistograms; 242 Vector<Histogram> m_SWPrefetchMachLatencyHistograms; 243 244 Histogram m_delayedCyclesHistogram; 245 Histogram m_delayedCyclesNonPFHistogram; 246 Vector<Histogram> m_delayedCyclesVCHistograms; 247 248 Histogram m_outstanding_requests; 249 Histogram m_outstanding_persistent_requests; 250 251 Histogram m_average_latency_estimate; 252 253 Map<Address, int>* m_watch_address_list_ptr; 254 // counts all initiated cache request including PUTs 255 int m_requests; 256 Map <string, int>* m_requestProfileMap_ptr; 257 258 // added for MemoryControl: 259 //added by SS 260 Vector < memory_control_profiler* > m_mc_profilers; 261 262 //added by SS 263 bool m_hot_lines; 264 bool m_all_instructions; 265}; 266 267// Output operator declaration 268ostream& operator<<(ostream& out, const Profiler& obj); 269 270// ******************* Definitions ******************* 271 272// Output operator definition 273extern inline 274ostream& operator<<(ostream& out, const Profiler& obj) 275{ 276 obj.print(out); 277 out << flush; 278 return out; 279} 280 281#endif //PROFILER_H 282 283 284