Profiler.hh revision 6876:a658c315512c 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30   This file has been modified by Kevin Moore and Dan Nussbaum of the
31   Scalable Systems Research Group at Sun Microsystems Laboratories
32   (http://research.sun.com/scalable/) to support the Adaptive
33   Transactional Memory Test Platform (ATMTP).
34
35   Please send email to atmtp-interest@sun.com with feedback, questions, or
36   to request future announcements about ATMTP.
37
38   ----------------------------------------------------------------------
39
40   File modification date: 2008-02-23
41
42   ----------------------------------------------------------------------
43*/
44
45/*
46 * Profiler.hh
47 *
48 * Description:
49 *
50 * $Id$
51 *
52 */
53
54#ifndef PROFILER_H
55#define PROFILER_H
56
57#include "mem/ruby/libruby.hh"
58
59#include "mem/ruby/common/Global.hh"
60#include "mem/protocol/GenericMachineType.hh"
61#include "mem/ruby/common/Histogram.hh"
62#include "mem/ruby/common/Consumer.hh"
63#include "mem/protocol/AccessModeType.hh"
64#include "mem/protocol/AccessType.hh"
65#include "mem/ruby/system/NodeID.hh"
66#include "mem/ruby/system/MachineID.hh"
67#include "mem/protocol/PrefetchBit.hh"
68#include "mem/ruby/common/Address.hh"
69#include "mem/ruby/common/Set.hh"
70#include "mem/protocol/CacheRequestType.hh"
71#include "mem/protocol/GenericRequestType.hh"
72#include "mem/ruby/system/MemoryControl.hh"
73
74#include "params/RubyProfiler.hh"
75#include "sim/sim_object.hh"
76
77class CacheMsg;
78class AddressProfiler;
79
80template <class KEY_TYPE, class VALUE_TYPE> class Map;
81
82struct memory_control_profiler {
83  long long int m_memReq;
84  long long int m_memBankBusy;
85  long long int m_memBusBusy;
86  long long int m_memTfawBusy;
87  long long int m_memReadWriteBusy;
88  long long int m_memDataBusBusy;
89  long long int m_memRefresh;
90  long long int m_memRead;
91  long long int m_memWrite;
92  long long int m_memWaitCycles;
93  long long int m_memInputQ;
94  long long int m_memBankQ;
95  long long int m_memArbWait;
96  long long int m_memRandBusy;
97  long long int m_memNotOld;
98  Vector<long long int> m_memBankCount;
99  int m_banks_per_rank;
100  int m_ranks_per_dimm;
101  int m_dimms_per_channel;
102};
103
104
105class Profiler : public SimObject, public Consumer {
106public:
107  // Constructors
108    typedef RubyProfilerParams Params;
109  Profiler(const Params *);
110
111  void init(const vector<string> & argv, vector<string> memory_control_names);
112
113  // Destructor
114  ~Profiler();
115
116  // Public Methods
117  void wakeup();
118
119  void setPeriodicStatsFile(const string& filename);
120  void setPeriodicStatsInterval(integer_t period);
121
122  void printStats(ostream& out, bool short_stats=false);
123  void printShortStats(ostream& out) { printStats(out, true); }
124  void printTraceStats(ostream& out) const;
125  void clearStats();
126  void printConfig(ostream& out) const;
127  void printResourceUsage(ostream& out) const;
128
129  AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
130  AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
131
132  void addAddressTraceSample(const CacheMsg& msg, NodeID id);
133
134  void profileRequest(const string& requestStr);
135  void profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner);
136
137  void profileMulticastRetry(const Address& addr, int count);
138
139  void profileFilterAction(int action);
140
141  void profileConflictingRequests(const Address& addr);
142  void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); }
143  void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); }
144  void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); }
145
146  void recordPrediction(bool wasGood, bool wasPredicted);
147
148  void startTransaction(int cpu);
149  void endTransaction(int cpu);
150  void profilePFWait(Time waitTime);
151
152  void controllerBusy(MachineID machID);
153  void bankBusy();
154  void missLatency(Time t, RubyRequestType type);
155  void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach);
156  void sequencerRequests(int num) { m_sequencer_requests.add(num); }
157
158  void profileTransition(const string& component, NodeID version, Address addr,
159                         const string& state, const string& event,
160                         const string& next_state, const string& note);
161  void profileMsgDelay(int virtualNetwork, int delayCycles);
162
163  void print(ostream& out) const;
164
165  int64 getTotalTransactionsExecuted() const;
166
167  void rubyWatch(int proc);
168  bool watchAddress(Address addr);
169
170  // return Ruby's start time
171  Time getRubyStartTime(){
172    return m_ruby_start;
173  }
174
175  // added for MemoryControl:
176  void profileMemReq(string name, int bank);
177  void profileMemBankBusy(string name);
178  void profileMemBusBusy(string name);
179  void profileMemTfawBusy(string name);
180  void profileMemReadWriteBusy(string name);
181  void profileMemDataBusBusy(string name);
182  void profileMemRefresh(string name);
183  void profileMemRead(string name);
184  void profileMemWrite(string name);
185  void profileMemWaitCycles(string name, int cycles);
186  void profileMemInputQ(string name, int cycles);
187  void profileMemBankQ(string name, int cycles);
188  void profileMemArbWait(string name, int cycles);
189  void profileMemRandBusy(string name);
190  void profileMemNotOld(string name);
191  //added by SS
192  bool getHotLines() { return m_hot_lines; }
193  bool getAllInstructions() { return m_all_instructions; }
194
195private:
196  //added by SS
197  vector<string> m_memory_control_names;
198
199  // Private copy constructor and assignment operator
200  Profiler(const Profiler& obj);
201  Profiler& operator=(const Profiler& obj);
202
203  // Data Members (m_ prefix)
204  AddressProfiler* m_address_profiler_ptr;
205  AddressProfiler* m_inst_profiler_ptr;
206
207  Vector<int64> m_instructions_executed_at_start;
208  Vector<int64> m_cycles_executed_at_start;
209
210  ostream* m_periodic_output_file_ptr;
211  integer_t m_stats_period;
212
213  Time m_ruby_start;
214  time_t m_real_time_start_time;
215
216  Vector<integer_t> m_perProcTotalMisses;
217  Vector<integer_t> m_perProcUserMisses;
218  Vector<integer_t> m_perProcSupervisorMisses;
219  Vector<integer_t> m_perProcStartTransaction;
220  Vector<integer_t> m_perProcEndTransaction;
221  Vector < Vector < integer_t > > m_busyControllerCount;
222  integer_t m_busyBankCount;
223  Histogram m_multicast_retry_histogram;
224
225  Histogram m_filter_action_histogram;
226  Histogram m_tbeProfile;
227
228  Histogram m_sequencer_requests;
229  Histogram m_read_sharing_histogram;
230  Histogram m_write_sharing_histogram;
231  Histogram m_all_sharing_histogram;
232  int64 m_cache_to_cache;
233  int64 m_memory_to_cache;
234
235  Histogram m_prefetchWaitHistogram;
236
237  Vector<Histogram> m_missLatencyHistograms;
238  Vector<Histogram> m_machLatencyHistograms;
239  Histogram m_allMissLatencyHistogram;
240
241  Histogram  m_allSWPrefetchLatencyHistogram;
242  Histogram  m_SWPrefetchL2MissLatencyHistogram;
243  Vector<Histogram> m_SWPrefetchLatencyHistograms;
244  Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
245
246  Histogram m_delayedCyclesHistogram;
247  Histogram m_delayedCyclesNonPFHistogram;
248  Vector<Histogram> m_delayedCyclesVCHistograms;
249
250  Histogram m_outstanding_requests;
251  Histogram m_outstanding_persistent_requests;
252
253  Histogram m_average_latency_estimate;
254
255  Map<Address, int>* m_watch_address_list_ptr;
256  // counts all initiated cache request including PUTs
257  int m_requests;
258  Map <string, int>* m_requestProfileMap_ptr;
259
260  // added for MemoryControl:
261  //added by SS
262  map< string, memory_control_profiler* > m_memory_control_profilers;
263
264  //added by SS
265  bool m_hot_lines;
266  bool m_all_instructions;
267};
268
269// Output operator declaration
270ostream& operator<<(ostream& out, const Profiler& obj);
271
272// ******************* Definitions *******************
273
274// Output operator definition
275extern inline
276ostream& operator<<(ostream& out, const Profiler& obj)
277{
278  obj.print(out);
279  out << flush;
280  return out;
281}
282
283#endif //PROFILER_H
284
285
286