Switch.hh revision 9858:f2417ecf5cc9
16145SN/A/* 26145SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 2911793Sbrandon.potter@amd.com/* 3011793Sbrandon.potter@amd.com * The actual modelled switch. It use the perfect switch and a 317832SN/A * Throttle object to control and bandwidth and timing *only for the 327832SN/A * output port*. So here we have un-realistic modelling, since the 339356Snilay@cs.wisc.edu * order of PerfectSwitch and Throttle objects get woke up affect the 348232SN/A * message timing. A more accurate model would be having two set of 357054SN/A * system states, one for this cycle, one for next cycle. And on the 368257SBrad.Beckmann@amd.com * cycle boundary swap the two set of states. 3711793Sbrandon.potter@amd.com */ 387054SN/A 396145SN/A#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 407055SN/A#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 417055SN/A 427054SN/A#include <iostream> 438257SBrad.Beckmann@amd.com#include <vector> 446145SN/A 456145SN/A#include "mem/packet.hh" 466145SN/A#include "mem/ruby/common/TypeDefines.hh" 476145SN/A#include "mem/ruby/network/BasicRouter.hh" 486145SN/A#include "params/Switch.hh" 496145SN/A 506145SN/Aclass MessageBuffer; 5111096Snilay@cs.wisc.educlass PerfectSwitch; 5211096Snilay@cs.wisc.educlass NetDest; 5311096Snilay@cs.wisc.educlass SimpleNetwork; 5411096Snilay@cs.wisc.educlass Throttle; 5511096Snilay@cs.wisc.edu 566145SN/Aclass Switch : public BasicRouter 576881SN/A{ 586881SN/A public: 596285SN/A typedef SwitchParams Params; 6011663Stushar@ece.gatech.edu Switch(const Params *p); 6111663Stushar@ece.gatech.edu ~Switch(); 6211663Stushar@ece.gatech.edu 6311663Stushar@ece.gatech.edu void init(); 6411663Stushar@ece.gatech.edu void addInPort(const std::vector<MessageBuffer*>& in); 6511663Stushar@ece.gatech.edu void addOutPort(const std::vector<MessageBuffer*>& out, 6611663Stushar@ece.gatech.edu const NetDest& routing_table_entry, Cycles link_latency, 6711663Stushar@ece.gatech.edu int bw_multiplier); 689594Snilay@cs.wisc.edu const Throttle* getThrottle(LinkID link_number) const; 699594Snilay@cs.wisc.edu const std::vector<Throttle*>* getThrottles() const; 708257SBrad.Beckmann@amd.com void clearRoutingTables(); 718257SBrad.Beckmann@amd.com void clearBuffers(); 728257SBrad.Beckmann@amd.com void reconfigureOutPort(const NetDest& routing_table_entry); 736881SN/A 7410078Snilay@cs.wisc.edu void printStats(std::ostream& out) const; 759869Sjthestness@gmail.com void clearStats(); 767054SN/A void print(std::ostream& out) const; 778257SBrad.Beckmann@amd.com void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; } 786145SN/A 798257SBrad.Beckmann@amd.com bool functionalRead(Packet *); 8011663Stushar@ece.gatech.edu uint32_t functionalWrite(Packet *); 8111663Stushar@ece.gatech.edu 8211663Stushar@ece.gatech.edu private: 8311663Stushar@ece.gatech.edu // Private copy constructor and assignment operator 847054SN/A Switch(const Switch& obj); 856145SN/A Switch& operator=(const Switch& obj); 8611663Stushar@ece.gatech.edu 879594Snilay@cs.wisc.edu PerfectSwitch* m_perfect_switch; 889594Snilay@cs.wisc.edu SimpleNetwork* m_network_ptr; 898257SBrad.Beckmann@amd.com std::vector<Throttle*> m_throttles; 9011663Stushar@ece.gatech.edu std::vector<MessageBuffer*> m_buffers_to_free; 9111663Stushar@ece.gatech.edu}; 926881SN/A 9311664Stushar@ece.gatech.eduinline std::ostream& 9411664Stushar@ece.gatech.eduoperator<<(std::ostream& out, const Switch& obj) 9511664Stushar@ece.gatech.edu{ 968257SBrad.Beckmann@amd.com obj.print(out); 978257SBrad.Beckmann@amd.com out << std::flush; 988257SBrad.Beckmann@amd.com return out; 9911663Stushar@ece.gatech.edu} 10011663Stushar@ece.gatech.edu 1018257SBrad.Beckmann@amd.com#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 10211663Stushar@ece.gatech.edu